diff options
author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:40 -0500 |
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committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:40 -0500 |
commit | 94561dd5268d139b721561166cbce94170701c2c (patch) | |
tree | 2e534ce3e0cdf0a9bbdec41978ef3bb775eb2929 /src/arch/x86/isa.cc | |
parent | d44f2f611ff51941a8702a33a0bc57d7f574e462 (diff) | |
download | gem5-94561dd5268d139b721561166cbce94170701c2c.tar.xz |
arch: Add support for invalidating TLBs when draining
This patch adds support for the memInvalidate() drain method. TLB
flushing is requested by calling the virtual flushAll() method on the
TLB.
Note: This patch renames invalidateAll() to flushAll() on x86 and
SPARC to make the interface consistent across all supported
architectures.
Diffstat (limited to 'src/arch/x86/isa.cc')
-rw-r--r-- | src/arch/x86/isa.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index 9dbab8c7e..852ce6bc8 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -191,8 +191,8 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) } } if (toggled.pg) { - tc->getITBPtr()->invalidateAll(); - tc->getDTBPtr()->invalidateAll(); + tc->getITBPtr()->flushAll(); + tc->getDTBPtr()->flushAll(); } //This must always be 1. newCR0.et = 1; @@ -208,15 +208,15 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) case MISCREG_CR2: break; case MISCREG_CR3: - tc->getITBPtr()->invalidateNonGlobal(); - tc->getDTBPtr()->invalidateNonGlobal(); + tc->getITBPtr()->flushNonGlobal(); + tc->getDTBPtr()->flushNonGlobal(); break; case MISCREG_CR4: { CR4 toggled = regVal[miscReg] ^ val; if (toggled.pae || toggled.pse || toggled.pge) { - tc->getITBPtr()->invalidateAll(); - tc->getDTBPtr()->invalidateAll(); + tc->getITBPtr()->flushAll(); + tc->getDTBPtr()->flushAll(); } } break; |