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| author | Gabe Black <gblack@eecs.umich.edu> | 2013-01-04 19:00:44 -0600 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2013-01-04 19:00:44 -0600 |
| commit | d1965af22045d2a62b1cd1bc473b836413d79b46 (patch) | |
| tree | 3b5a67ba03489fc8789923b724bc04f04070bea3 /src/arch/x86/isa.cc | |
| parent | 63b10907ef822aa6873d7f4f4d1ee849a188b2c4 (diff) | |
| download | gem5-d1965af22045d2a62b1cd1bc473b836413d79b46.tar.xz | |
X86: Move address based decode caching in front of the predecoder.
The predecoder in x86 does a lot of work, most of which can be skipped if the
decoder cache is put in front of it.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/arch/x86/isa.cc')
| -rw-r--r-- | src/arch/x86/isa.cc | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index 5305b1058..1a9b39840 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -28,6 +28,7 @@ * Authors: Gabe Black */ +#include "arch/x86/decoder.hh" #include "arch/x86/isa.hh" #include "arch/x86/tlb.hh" #include "cpu/base.hh" @@ -39,7 +40,8 @@ namespace X86ISA void ISA::updateHandyM5Reg(Efer efer, CR0 cr0, - SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags) + SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags, + ThreadContext *tc) { HandyM5Reg m5reg = 0; if (efer.lma) { @@ -94,6 +96,8 @@ ISA::updateHandyM5Reg(Efer efer, CR0 cr0, } regVal[MISCREG_M5_REG] = m5reg; + if (tc) + tc->getDecoderPtr()->setM5Reg(m5reg); } void @@ -184,7 +188,8 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) newCR0, regVal[MISCREG_CS_ATTR], regVal[MISCREG_SS_ATTR], - regVal[MISCREG_RFLAGS]); + regVal[MISCREG_RFLAGS], + tc); } break; case MISCREG_CR2: @@ -225,7 +230,8 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) regVal[MISCREG_CR0], newCSAttr, regVal[MISCREG_SS_ATTR], - regVal[MISCREG_RFLAGS]); + regVal[MISCREG_RFLAGS], + tc); } break; case MISCREG_SS_ATTR: @@ -233,7 +239,8 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) regVal[MISCREG_CR0], regVal[MISCREG_CS_ATTR], val, - regVal[MISCREG_RFLAGS]); + regVal[MISCREG_RFLAGS], + tc); break; // These segments always actually use their bases, or in other words // their effective bases must stay equal to their actual bases. @@ -340,7 +347,8 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) regVal[MISCREG_CR0], regVal[MISCREG_CS_ATTR], regVal[MISCREG_SS_ATTR], - regVal[MISCREG_RFLAGS]); + regVal[MISCREG_RFLAGS], + tc); return; default: break; @@ -363,7 +371,8 @@ ISA::unserialize(EventManager *em, Checkpoint * cp, regVal[MISCREG_CR0], regVal[MISCREG_CS_ATTR], regVal[MISCREG_SS_ATTR], - regVal[MISCREG_RFLAGS]); + regVal[MISCREG_RFLAGS], + NULL); } } |