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authorGabe Black <gblack@eecs.umich.edu>2009-07-17 00:29:42 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-17 00:29:42 -0700
commitdf378285f8e2aaf8e1a1bd54f862ed7c7a073e28 (patch)
treea1b329e2b480c008e539ab3d432a151c3ab5a514 /src/arch/x86/isa.cc
parente557b4beb570c2019d01da6cb1036dad5853cb60 (diff)
downloadgem5-df378285f8e2aaf8e1a1bd54f862ed7c7a073e28.tar.xz
X86: Shift some register flattening work into the decoder.
Diffstat (limited to 'src/arch/x86/isa.cc')
-rw-r--r--src/arch/x86/isa.cc22
1 files changed, 0 insertions, 22 deletions
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index d19a2a6cc..06a656efc 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -28,7 +28,6 @@
* Authors: Gabe Black
*/
-#include "arch/x86/floatregs.hh"
#include "arch/x86/isa.hh"
#include "arch/x86/tlb.hh"
#include "cpu/base.hh"
@@ -355,25 +354,4 @@ ISA::unserialize(EventManager *em, Checkpoint * cp,
UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
}
-int
-ISA::flattenIntIndex(int reg)
-{
- //If we need to fold over the index to match byte semantics, do that.
- //Otherwise, just strip off any extra bits and pass it through.
- if (reg & (1 << 6))
- return (reg & (~(1 << 6) - 0x4));
- else
- return (reg & ~(1 << 6));
-}
-
-int
-ISA::flattenFloatIndex(int reg)
-{
- if (reg >= NUM_FLOATREGS) {
- int top = readMiscRegNoEffect(MISCREG_X87_TOP);
- reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
- }
- return reg;
-}
-
}