diff options
| author | Gabe Black <gabeblack@google.com> | 2018-11-20 16:58:19 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-31 11:04:13 +0000 |
| commit | b859a7030d883cc208347387b19285c53b64fb54 (patch) | |
| tree | 3b70cba6c8c102bb07476ee69b0ce38ca6f86a09 /src/arch/x86/isa.cc | |
| parent | ad775e013572aeb06ccff949dfd2cf7fffb5454f (diff) | |
| download | gem5-b859a7030d883cc208347387b19285c53b64fb54.tar.xz | |
x86: Stop using/defining some ISA specific register types.
These have been replaced with the generic RegVal type.
Change-Id: I75c1134212067dea43aa0903d813633e06f3d6c6
Reviewed-on: https://gem5-review.googlesource.com/c/14476
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86/isa.cc')
| -rw-r--r-- | src/arch/x86/isa.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index a866b950f..d96a85893 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -107,7 +107,7 @@ ISA::clear() { // Blank everything. 0 might not be an appropriate value for some things, // but it is for most. - memset(regVal, 0, NumMiscRegs * sizeof(MiscReg)); + memset(regVal, 0, NumMiscRegs * sizeof(RegVal)); regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16); regVal[MISCREG_DR7] = 1 << 10; } @@ -124,7 +124,7 @@ ISA::params() const return dynamic_cast<const Params *>(_params); } -MiscReg +RegVal ISA::readMiscRegNoEffect(int miscReg) const { // Make sure we're not dealing with an illegal control register. @@ -135,7 +135,7 @@ ISA::readMiscRegNoEffect(int miscReg) const return regVal[miscReg]; } -MiscReg +RegVal ISA::readMiscReg(int miscReg, ThreadContext * tc) { if (miscReg == MISCREG_TSC) { @@ -143,8 +143,8 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc) } if (miscReg == MISCREG_FSW) { - MiscReg fsw = regVal[MISCREG_FSW]; - MiscReg top = regVal[MISCREG_X87_TOP]; + RegVal fsw = regVal[MISCREG_FSW]; + RegVal top = regVal[MISCREG_X87_TOP]; return insertBits(fsw, 13, 11, top); } @@ -152,7 +152,7 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc) } void -ISA::setMiscRegNoEffect(int miscReg, MiscReg val) +ISA::setMiscRegNoEffect(int miscReg, RegVal val) { // Make sure we're not dealing with an illegal control register. // Instructions should filter out these indexes, and nothing else should @@ -194,9 +194,9 @@ ISA::setMiscRegNoEffect(int miscReg, MiscReg val) } void -ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) +ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc) { - MiscReg newVal = val; + RegVal newVal = val; switch(miscReg) { case MISCREG_CR0: |