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author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:35 -0500 |
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committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:35 -0500 |
commit | 3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98 (patch) | |
tree | a736f3746d5c38bdc98d6fb8589113556271d486 /src/arch/x86/isa.hh | |
parent | 69d419f31383ac7801e1debb62d5bbf7cb899e3c (diff) | |
download | gem5-3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98.tar.xz |
arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.
This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
Diffstat (limited to 'src/arch/x86/isa.hh')
-rw-r--r-- | src/arch/x86/isa.hh | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh index 7b0c7b61a..39ed68ea5 100644 --- a/src/arch/x86/isa.hh +++ b/src/arch/x86/isa.hh @@ -38,14 +38,16 @@ #include "arch/x86/regs/misc.hh" #include "arch/x86/registers.hh" #include "base/types.hh" +#include "sim/sim_object.hh" class Checkpoint; class EventManager; class ThreadContext; +struct X86ISAParams; namespace X86ISA { - class ISA + class ISA : public SimObject { protected: MiscReg regVal[NUM_MISCREGS]; @@ -54,12 +56,12 @@ namespace X86ISA ThreadContext *tc); public: + typedef X86ISAParams Params; + void clear(); - ISA() - { - clear(); - } + ISA(Params *p); + const Params *params() const; MiscReg readMiscRegNoEffect(int miscReg); MiscReg readMiscReg(int miscReg, ThreadContext *tc); |