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| author | Gabe Black <gblack@eecs.umich.edu> | 2013-01-04 19:00:44 -0600 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2013-01-04 19:00:44 -0600 |
| commit | d1965af22045d2a62b1cd1bc473b836413d79b46 (patch) | |
| tree | 3b5a67ba03489fc8789923b724bc04f04070bea3 /src/arch/x86/isa.hh | |
| parent | 63b10907ef822aa6873d7f4f4d1ee849a188b2c4 (diff) | |
| download | gem5-d1965af22045d2a62b1cd1bc473b836413d79b46.tar.xz | |
X86: Move address based decode caching in front of the predecoder.
The predecoder in x86 does a lot of work, most of which can be skipped if the
decoder cache is put in front of it.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/arch/x86/isa.hh')
| -rw-r--r-- | src/arch/x86/isa.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh index 463a249a4..7b0c7b61a 100644 --- a/src/arch/x86/isa.hh +++ b/src/arch/x86/isa.hh @@ -50,7 +50,8 @@ namespace X86ISA protected: MiscReg regVal[NUM_MISCREGS]; void updateHandyM5Reg(Efer efer, CR0 cr0, - SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags); + SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags, + ThreadContext *tc); public: void clear(); |