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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-17 00:29:42 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-17 00:29:42 -0700 |
commit | df378285f8e2aaf8e1a1bd54f862ed7c7a073e28 (patch) | |
tree | a1b329e2b480c008e539ab3d432a151c3ab5a514 /src/arch/x86/isa.hh | |
parent | e557b4beb570c2019d01da6cb1036dad5853cb60 (diff) | |
download | gem5-df378285f8e2aaf8e1a1bd54f862ed7c7a073e28.tar.xz |
X86: Shift some register flattening work into the decoder.
Diffstat (limited to 'src/arch/x86/isa.hh')
-rw-r--r-- | src/arch/x86/isa.hh | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh index 285f0aa82..8d3b110c6 100644 --- a/src/arch/x86/isa.hh +++ b/src/arch/x86/isa.hh @@ -31,6 +31,7 @@ #ifndef __ARCH_X86_ISA_HH__ #define __ARCH_X86_ISA_HH__ +#include "arch/x86/floatregs.hh" #include "arch/x86/miscregs.hh" #include "arch/x86/registers.hh" #include "base/types.hh" @@ -65,8 +66,21 @@ namespace X86ISA void setMiscRegNoEffect(int miscReg, MiscReg val); void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc); - int flattenIntIndex(int reg); - int flattenFloatIndex(int reg); + int + flattenIntIndex(int reg) + { + return reg & ~(1 << 6); + } + + int + flattenFloatIndex(int reg) + { + if (reg >= NUM_FLOATREGS) { + reg = FLOATREG_STACK(reg - NUM_FLOATREGS, + regVal[MISCREG_X87_TOP]); + } + return reg; + } void serialize(EventManager *em, std::ostream &os); void unserialize(EventManager *em, Checkpoint *cp, |