Break out the one and two byte opcodes into different files. Also change what bits decode is done on to reflect where clumps of instructions are.

--HG--
extra : convert_revision : 8768676eac25e6a4f0dc50ce2dc576bdcdd6e025

1 files changed, 181 insertions, 0 deletions

diff --git a/src/arch/x86/isa/base.isa b/src/arch/x86/isa/base.isa
new file mode 100644
index 000000000..4776f7a7e
--- /dev/null
+++ b/src/arch/x86/isa/base.isa
@@ -0,0 +1,181 @@
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use.  Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+//     Director of Intellectual Property Licensing
+//     Office of Strategy and Technology
+//     Hewlett-Packard Company
+//     1501 Page Mill Road
+//     Palo Alto, California  94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.  Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution.  Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.  No right of
+// sublicense is granted herewith.  Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses.  Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+////////////////////////////////////////////////////////////////////
+//
+// Base class for sparc instructions, and some support functions
+//
+
+output header {{
+
+        /**
+         * Base class for all X86 static instructions.
+         */
+        class X86StaticInst : public StaticInst
+        {
+          protected:
+            // Constructor.
+            X86StaticInst(const char *mnem,
+                 ExtMachInst _machInst, OpClass __opClass)
+                    : StaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+            std::string generateDisassembly(Addr pc,
+                const SymbolTable *symtab) const;
+
+            void printReg(std::ostream &os, int reg) const;
+            void printSrcReg(std::ostream &os, int reg) const;
+            void printDestReg(std::ostream &os, int reg) const;
+        };
+}};
+
+output decoder {{
+
+        inline void printMnemonic(std::ostream &os, const char * mnemonic)
+        {
+            ccprintf(os, "\t%s   ", mnemonic);
+        }
+
+        void
+        X86StaticInst::printSrcReg(std::ostream &os, int reg) const
+        {
+            if(_numSrcRegs > reg)
+                printReg(os, _srcRegIdx[reg]);
+        }
+
+        void
+        X86StaticInst::printDestReg(std::ostream &os, int reg) const
+        {
+            if(_numDestRegs > reg)
+                printReg(os, _destRegIdx[reg]);
+        }
+
+        void
+        X86StaticInst::printReg(std::ostream &os, int reg) const
+        {
+            if (reg < FP_Base_DepTag) {
+                //FIXME These should print differently depending on the
+                //mode etc, but for now this will get the point across
+                switch (reg) {
+                  case INTREG_RAX:
+                    ccprintf(os, "rax");
+                    break;
+                  case INTREG_RBX:
+                    ccprintf(os, "rbx");
+                    break;
+                  case INTREG_RCX:
+                    ccprintf(os, "rcx");
+                    break;
+                  case INTREG_RDX:
+                    ccprintf(os, "rdx");
+                    break;
+                  case INTREG_RSP:
+                    ccprintf(os, "rsp");
+                    break;
+                  case INTREG_RBP:
+                    ccprintf(os, "rbp");
+                    break;
+                  case INTREG_RSI:
+                    ccprintf(os, "rsi");
+                    break;
+                  case INTREG_RDI:
+                    ccprintf(os, "rdi");
+                    break;
+                  case INTREG_R8W:
+                    ccprintf(os, "r8");
+                    break;
+                  case INTREG_R9W:
+                    ccprintf(os, "r9");
+                    break;
+                  case INTREG_R10W:
+                    ccprintf(os, "r10");
+                    break;
+                  case INTREG_R11W:
+                    ccprintf(os, "r11");
+                    break;
+                  case INTREG_R12W:
+                    ccprintf(os, "r12");
+                    break;
+                  case INTREG_R13W:
+                    ccprintf(os, "r13");
+                    break;
+                  case INTREG_R14W:
+                    ccprintf(os, "r14");
+                    break;
+                  case INTREG_R15W:
+                    ccprintf(os, "r15");
+                    break;
+                }
+            } else if (reg < Ctrl_Base_DepTag) {
+                ccprintf(os, "%%f%d", reg - FP_Base_DepTag);
+            } else {
+                switch (reg - Ctrl_Base_DepTag) {
+                  default:
+                    ccprintf(os, "%%ctrl%d", reg - Ctrl_Base_DepTag);
+                }
+            }
+        }
+
+        std::string X86StaticInst::generateDisassembly(Addr pc,
+            const SymbolTable *symtab) const
+        {
+            std::stringstream ss;
+
+            printMnemonic(ss, mnemonic);
+
+            return ss.str();
+        }
+}};