x86: Rework opcode parsing to support 3 byte opcodes properly.

Instead of counting the number of opcode bytes in an instruction and recording
each byte before the actual opcode, we can represent the path we took to get to
the actual opcode byte by using a type code. That has a couple of advantages.
First, we can disambiguate the properties of opcodes of the same length which
have different properties. Second, it reduces the amount of data stored in an
ExtMachInst, making them slightly easier/faster to create and process. This
also adds some flexibility as far as how different types of opcodes are
handled, which might come in handy if we decide to support VEX or XOP
instructions.

This change also adds tables to support properly decoding 3 byte opcodes.
Before we would fall off the end of some arrays, on top of the ambiguity
described above.

This change doesn't measureably affect performance on the twolf benchmark.

--HG--
rename : src/arch/x86/isa/decoder/three_byte_opcodes.isa => src/arch/x86/isa/decoder/three_byte_0f38_opcodes.isa
rename : src/arch/x86/isa/decoder/three_byte_opcodes.isa => src/arch/x86/isa/decoder/three_byte_0f3a_opcodes.isa

1 files changed, 1 insertions, 3 deletions

diff --git a/src/arch/x86/isa/bitfields.isa b/src/arch/x86/isa/bitfields.isa
index a7753ba3d..e2751a8ef 100644
--- a/src/arch/x86/isa/bitfields.isa
+++ b/src/arch/x86/isa/bitfields.isa
@@ -59,9 +59,7 @@ def bitfield LEGACY_ADDR legacy.addr;
 def bitfield LEGACY_SEG legacy.seg;
 
 // Pieces of the opcode
-def bitfield OPCODE_NUM opcode.num;
-def bitfield OPCODE_PREFIXA opcode.prefixA;
-def bitfield OPCODE_PREFIXB opcode.prefixB;
+def bitfield OPCODE_TYPE opcode.type;
 def bitfield OPCODE_OP opcode.op;
 //The top 5 bits of the opcode tend to split the instructions into groups
 def bitfield OPCODE_OP_TOP5 opcode.op.top5;