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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2015-10-06 17:26:50 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2015-10-06 17:26:50 -0700 |
| commit | a2c875c746a7b9b5dcb94fd93d94ab70286dbbb4 (patch) | |
| tree | 03ac1c0befec0a164e233b655759efac0f3207c0 /src/arch/x86/isa/decoder/two_byte_opcodes.isa | |
| parent | 57b9f53afa5660152a77b7f3b7affb39f5b0e176 (diff) | |
| download | gem5-a2c875c746a7b9b5dcb94fd93d94ab70286dbbb4.tar.xz | |
x86: implement rcpps and rcpss SSE insts
These are packed single-precision approximate reciprocal operations,
vector and scalar versions, respectively.
This code was basically developed by copying the code for
sqrtps and sqrtss. The mrcp micro-op was simplified relative to
msqrt since there are no double-precision versions of this operation.
Diffstat (limited to 'src/arch/x86/isa/decoder/two_byte_opcodes.isa')
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index 0ba7434e8..4a21e2900 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -463,7 +463,7 @@ 0x0: MOVMSKPS(Gd,VRo); 0x1: SQRTPS(Vo,Wo); 0x2: WarnUnimpl::rqsrtps_Vo_Wo(); - 0x3: WarnUnimpl::rcpps_Vo_Wo(); + 0x3: RCPPS(Vo,Wo); 0x4: ANDPS(Vo,Wo); 0x5: ANDNPS(Vo,Wo); 0x6: ORPS(Vo,Wo); @@ -473,7 +473,7 @@ 0x4: decode OPCODE_OP_BOTTOM3 { 0x1: SQRTSS(Vd,Wd); 0x2: WarnUnimpl::rsqrtss_Vd_Wd(); - 0x3: WarnUnimpl::rcpss_Vd_Wd(); + 0x3: RCPSS(Vd,Wd); default: UD2(); } // operand size (0x66) |