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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-04-04 14:31:59 +0000 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-04-04 14:31:59 +0000 |
| commit | 4285990a96bad869bc1046f28f99cf7f4b5c8de0 (patch) | |
| tree | 80b92e77e93ef76d5b8a154ad71813727e6e2be9 /src/arch/x86/isa/decoder | |
| parent | 7f5409f2babd4fe26c364aedf7faf4cdcb0eb3f0 (diff) | |
| download | gem5-4285990a96bad869bc1046f28f99cf7f4b5c8de0.tar.xz | |
Reworking how x86's isa description works. I'm adopting the following definitions to make figuring out what's what a little easier:
MicroOp: A single operation actually implemented in hardware.
MacroOp: A collection of microops which are executed as a unit.
Instruction: An architected instruction which can be implemented with a macroop or a microop.
--HG--
extra : convert_revision : 1cfc8409cc686c75220767839f55a30551aa6f13
Diffstat (limited to 'src/arch/x86/isa/decoder')
| -rw-r--r-- | src/arch/x86/isa/decoder/one_byte_opcodes.isa | 22 |
1 files changed, 8 insertions, 14 deletions
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa index f7e6e3994..938904bc1 100644 --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa @@ -61,15 +61,12 @@ 0x1: decode OPCODE_OP_TOP5 { format WarnUnimpl { 0x00: decode OPCODE_OP_BOTTOM3 { - 0x4: TaggedOp::add({{AddI %0 %0}}, [rAl]); - 0x5: TaggedOp::add({{AddI %0 %0}}, [rAx]); + 0x4: Inst::addI(rAl,Ib); + 0x5: Inst::addI(rAx,Iz); 0x6: push_ES(); 0x7: pop_ES(); - default: MultiOp::add( - {{Add %0 %0 %1}}, - OPCODE_OP_BOTTOM3, - [[Eb,Gb],[Ev,Gv], - [Gb,Eb],[Gv,Ev]]); + default: MultiInst::add(OPCODE_OP_BOTTOM3, + [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]); } 0x01: decode OPCODE_OP_BOTTOM3 { 0x0: or_Eb_Gb(); @@ -126,16 +123,13 @@ 0x7: das(); } 0x06: decode OPCODE_OP_BOTTOM3 { - 0x4: TaggedOp::xor({{XorI %0 %0}}, [rAl]); - 0x5: TaggedOp::xor({{XorI %0 %0}}, [rAx]); + 0x4: Inst::xorI(rAl,Ib); + 0x5: Inst::xorI(rAx,Iz); 0x6: M5InternalError::error( {{"Tried to execute the SS segment override prefix!"}}); 0x7: aaa(); - default: MultiOp::xor( - {{Xor %0 %0 %1}}, - OPCODE_OP_BOTTOM3, - [[Eb,Gb],[Ev,Gv], - [Gb,Eb],[Gv,Ev]]); + default: MultiInst::xor(OPCODE_OP_BOTTOM3, + [Eb,Gb],[Ev,Gv],[Gb,Eb],[Gv,Ev]); } 0x07: decode OPCODE_OP_BOTTOM3 { 0x0: cmp_Eb_Gb(); |