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| author | Gabe Black <gabeblack@google.com> | 2017-08-24 17:06:36 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-08-28 20:56:33 +0000 |
| commit | 4e939a7b4d33088bda1fe0c2871be2bf61276e21 (patch) | |
| tree | c17270f363674fbc73e0294d94545d9c24a43008 /src/arch/x86/isa/decoder | |
| parent | 544eba88b94b693319eca6a2569f38449465b678 (diff) | |
| download | gem5-4e939a7b4d33088bda1fe0c2871be2bf61276e21.tar.xz | |
x86: Use the new CondInst format for moves to/from control registers.
The condition is whether the control register index is valid.
Change-Id: I8a225fcfd4955032b5bbf7d3392ee5bcc7d6bc64
Reviewed-on: https://gem5-review.googlesource.com/4581
Reviewed-by: Michael LeBeane <Michael.Lebeane@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86/isa/decoder')
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index 97c3dd688..8b8756823 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -360,9 +360,11 @@ 0x04: decode LEGACY_DECODEVAL { // no prefix 0x0: decode OPCODE_OP_BOTTOM3 { - 0x0: MOV(Rd,Cd); + 0x0: CondInst::MOV( + {{isValidMiscReg(MISCREG_CR(MODRM_RM))}},Rd,Cd); 0x1: MOV(Rd,Dd); - 0x2: MOV(Cd,Rd); + 0x2: CondInst::MOV( + {{isValidMiscReg(MISCREG_CR(MODRM_REG))}},Cd,Rd); 0x3: MOV(Dd,Rd); default: UD2(); } |