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| author | Maxime Martinasso <maxime.cscs@gmail.com> | 2015-01-03 17:51:48 -0600 |
|---|---|---|
| committer | Maxime Martinasso <maxime.cscs@gmail.com> | 2015-01-03 17:51:48 -0600 |
| commit | 5a5416d575f68e416ebe713ad76dc468a59ac23c (patch) | |
| tree | edebb20dcac36135e1a72ce824e55bac6f5e1348 /src/arch/x86/isa/decoder | |
| parent | 02c376ac44584484268bd714a45fa0f0265a896a (diff) | |
| download | gem5-5a5416d575f68e416ebe713ad76dc468a59ac23c.tar.xz | |
x86: implements the simd128 ADDSUBPD instruction
This patch implements the simd128 ADDSUBPD instruction for the x86 architecture.
Tested with a simple program in assembly language which executes the
instruction. Checked that different versions of the instruction are executed
by using the execution tracing option.
Committed by: Nilay Vaish <nilay@cs.wisc.edu
Diffstat (limited to 'src/arch/x86/isa/decoder')
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index e1b20feb1..dfc328c4b 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -903,7 +903,7 @@ } // operand size (0x66) 0x1: decode OPCODE_OP_BOTTOM3 { - 0x0: WarnUnimpl::addsubpd_Vo_Wo(); + 0x0: ADDSUBPD(Vo,Wo); 0x1: PSRLW(Vo,Wo); 0x2: PSRLD(Vo,Wo); 0x3: PSRLQ(Vo,Wo); |