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| author | Vince Weaver <vince@csl.cornell.edu> | 2009-10-21 13:40:43 -0400 |
|---|---|---|
| committer | Vince Weaver <vince@csl.cornell.edu> | 2009-10-21 13:40:43 -0400 |
| commit | 14691148cd9300ed7a23dd889b9c0173124b30eb (patch) | |
| tree | 4c73311d2302e94b9aed67ae70d36e184614b45b /src/arch/x86/isa/decoder | |
| parent | 5b6f707a008b4312fd02a4383bf107adfa677d33 (diff) | |
| download | gem5-14691148cd9300ed7a23dd889b9c0173124b30eb.tar.xz | |
Implement X86 sse2 movdqu and movdqa instructions
The movdqa instruction should enforce 16-byte alignment.
This implementation does not do that.
These instructions are needed for most of x86_64 spec2k to run.
Diffstat (limited to 'src/arch/x86/isa/decoder')
| -rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index c23eeccab..27aabaccc 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -604,7 +604,7 @@ } // repe (0xF3) 0x4: decode OPCODE_OP_BOTTOM3 { - 0x7: WarnUnimpl::movdqu_Vo_Wo(); + 0x7: MOVDQU(Vo,Wo); default: UD2(); } // operand size (0x66) @@ -616,7 +616,7 @@ 0x4: PUNPCKLQDQ(Vo,Wq); 0x5: PUNPCKHQDQ(Vo,Wq); 0x6: WarnUnimpl::movd_Vo_Ed(); - 0x7: WarnUnimpl::movdqa_Vo_Wo(); + 0x7: MOVDQA(Vo,Wo); } default: UD2(); } @@ -702,7 +702,7 @@ // repe (0xF3) 0x4: decode OPCODE_OP_BOTTOM3 { 0x6: MOVQ(Vq,Wq); - 0x7: WarnUnimpl::movdqu_Wo_Vo(); + 0x7: MOVDQU(Wo,Vo); default: UD2(); } // operand size (0x66) @@ -710,7 +710,7 @@ 0x4: WarnUnimpl::haddpd_Vo_Wo(); 0x5: WarnUnimpl::hsubpd_Vo_Wo(); 0x6: WarnUnimpl::movd_Ed_Vd(); - 0x7: WarnUnimpl::movdqa_Wo_Vo(); + 0x7: MOVDQA(Wo,Vo); default: UD2(); } // repne (0xF2) |