X86: Start implementing segmentation support.

Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.

--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9

1 files changed, 44 insertions, 44 deletions

diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
index de4996f54..87fbb796c 100644
--- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
@@ -68,45 +68,45 @@ def macroop ADD_R_I
 def macroop ADD_M_I
 {
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [scale, index, base], disp
+    st t1, seg, sib, disp
 };
 
 def macroop ADD_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [0, t0, t7], disp
+    st t1, seg, riprel, disp
 };
 
 def macroop ADD_M_R
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [scale, index, base], disp
+    st t1, seg, sib, disp
 };
 
 def macroop ADD_P_R
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [0, t0, t7], disp
+    st t1, seg, riprel, disp
 };
 
 def macroop ADD_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop ADD_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
@@ -123,47 +123,47 @@ def macroop SUB_R_I
 
 def macroop SUB_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SUB_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SUB_M_I
 {
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [scale, index, base], disp
+    st t1, seg, sib, disp
 };
 
 def macroop SUB_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [0, t0, t7], disp
+    st t1, seg, riprel, disp
 };
 
 def macroop SUB_M_R
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [scale, index, base], disp
+    st t1, seg, sib, disp
 };
 
 def macroop SUB_P_R
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [0, t0, t7], disp
+    st t1, seg, riprel, disp
 };
 
 def macroop ADC_R_R
@@ -180,45 +180,45 @@ def macroop ADC_R_I
 def macroop ADC_M_I
 {
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [scale, index, base], disp
+    st t1, seg, sib, disp
 };
 
 def macroop ADC_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [0, t0, t7], disp
+    st t1, seg, riprel, disp
 };
 
 def macroop ADC_M_R
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [scale, index, base], disp
+    st t1, seg, sib, disp
 };
 
 def macroop ADC_P_R
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [0, t0, t7], disp
+    st t1, seg, riprel, disp
 };
 
 def macroop ADC_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop ADC_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
@@ -235,47 +235,47 @@ def macroop SBB_R_I
 
 def macroop SBB_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SBB_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
 };
 
 def macroop SBB_M_I
 {
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [scale, index, base], disp
+    st t1, seg, sib, disp
 };
 
 def macroop SBB_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [0, t0, t7], disp
+    st t1, seg, riprel, disp
 };
 
 def macroop SBB_M_R
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [scale, index, base], disp
+    st t1, seg, sib, disp
 };
 
 def macroop SBB_P_R
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
-    st t1, ds, [0, t0, t7], disp
+    st t1, seg, riprel, disp
 };
 
 def macroop NEG_R
@@ -285,16 +285,16 @@ def macroop NEG_R
 
 def macroop NEG_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
-    st t1, ds, [scale, index, base], disp
+    st t1, seg, sib, disp
 };
 
 def macroop NEG_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
-    st t1, ds, [0, t0, t7], disp
+    st t1, seg, riprel, disp
 };
 '''