X86: Start implementing segmentation support.

Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.

--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9

1 files changed, 10 insertions, 10 deletions

diff --git a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
index f53fa8f05..2a8024eee 100644
--- a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
+++ b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
@@ -61,17 +61,17 @@ def macroop INC_R
 
 def macroop INC_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
-    st t1, ds, [scale, index, base], disp
+    st t1, seg, sib, disp
 };
 
 def macroop INC_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
-    addi reg, reg, 1, flags=(OF, SF, ZF, AF, PF)
-    st t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
+    addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
+    st t1, seg, riprel, disp
 };
 
 def macroop DEC_R
@@ -81,16 +81,16 @@ def macroop DEC_R
 
 def macroop DEC_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
-    st t1, ds, [scale, index, base], disp
+    st t1, seg, sib, disp
 };
 
 def macroop DEC_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
-    subi reg, reg, 1, flags=(OF, SF, ZF, AF, PF)
-    st t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
+    subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
+    st t1, seg, riprel, disp
 };
 '''