X86: Start implementing segmentation support.

Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.

--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9

1 files changed, 4 insertions, 4 deletions

diff --git a/src/arch/x86/isa/insts/compare_and_test/test.py b/src/arch/x86/isa/insts/compare_and_test/test.py
index 8da33899a..2b4bf7b9a 100644
--- a/src/arch/x86/isa/insts/compare_and_test/test.py
+++ b/src/arch/x86/isa/insts/compare_and_test/test.py
@@ -56,14 +56,14 @@
 microcode = '''
 def macroop TEST_M_R
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     and t0, t1, reg, flags=(SF, ZF, PF)
 };
 
 def macroop TEST_P_R
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     and t0, t1, reg, flags=(SF, ZF, PF)
 };
 
@@ -74,7 +74,7 @@ def macroop TEST_R_R
 
 def macroop TEST_M_I
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     limm t2, imm
     and t0, t1, t2, flags=(SF, ZF, PF)
 };
@@ -82,7 +82,7 @@ def macroop TEST_M_I
 def macroop TEST_P_I
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     limm t2, imm
     and t0, t1, t2, flags=(SF, ZF, PF)
 };