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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-22 09:24:07 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-22 09:24:07 -0700 |
| commit | bdd5fd20fb19eb52ef812cd284094e5513646e36 (patch) | |
| tree | ea6adc5417a2e40a561409db86211e48e59ae3de /src/arch/x86/isa/insts/control_transfer/call.py | |
| parent | eff122797b5bc735c6d7c797be691c0fa02032e3 (diff) | |
| download | gem5-bdd5fd20fb19eb52ef812cd284094e5513646e36.tar.xz | |
Fixes to hitLatency, blocking, buffer allocation.
Single-cpu timing mode seems to work now.
--HG--
extra : convert_revision : 720f6172df18a1c941e5bd0e8fdfbd686c13c7ad
Diffstat (limited to 'src/arch/x86/isa/insts/control_transfer/call.py')
0 files changed, 0 insertions, 0 deletions