diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:12:54 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:12:54 -0700 |
| commit | e410a925df8d37f386c97dc7cdd9a78347ce4700 (patch) | |
| tree | b4102987453b1303051dfeea61aa1a45c2e5e75f /src/arch/x86/isa/insts/control_transfer/call.py | |
| parent | ced6cbcccf4540358093f060dad4d59ad6557d6a (diff) | |
| download | gem5-e410a925df8d37f386c97dc7cdd9a78347ce4700.tar.xz | |
X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
Diffstat (limited to 'src/arch/x86/isa/insts/control_transfer/call.py')
| -rw-r--r-- | src/arch/x86/isa/insts/control_transfer/call.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/insts/control_transfer/call.py b/src/arch/x86/isa/insts/control_transfer/call.py index c5bb66e58..504e9ab0a 100644 --- a/src/arch/x86/isa/insts/control_transfer/call.py +++ b/src/arch/x86/isa/insts/control_transfer/call.py @@ -83,7 +83,7 @@ def macroop CALL_NEAR_M .adjust_env oszIn64Override rdip t7 - ld t1, ds, [scale, index, base], disp + ld t1, seg, sib, disp subi rsp, rsp, dsz st t7, ss, [0, t0, rsp] wripi t1, 0 @@ -95,7 +95,7 @@ def macroop CALL_NEAR_P .adjust_env oszIn64Override rdip t7 - ld t1, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp subi rsp, rsp, dsz st t7, ss, [0, t0, rsp] wripi t1, 0 |