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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:07:42 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:07:42 -0700 |
| commit | ced6cbcccf4540358093f060dad4d59ad6557d6a (patch) | |
| tree | 86e917f20b51b2afcddfc1d0ffd8192eaca13af1 /src/arch/x86/isa/insts/control_transfer/conditional_jump.py | |
| parent | 0e6be2a9b16660903306b2762e69a2678a54a6ba (diff) | |
| download | gem5-ced6cbcccf4540358093f060dad4d59ad6557d6a.tar.xz | |
X86: Create a base enum value for indexing into a region of the miscregs.
This lets you index into a group of registers without having to know
explicitly which one is the lowest in that group.
--HG--
extra : convert_revision : e3cad25a1c5910955204c37177b049ca9834cfd9
Diffstat (limited to 'src/arch/x86/isa/insts/control_transfer/conditional_jump.py')
0 files changed, 0 insertions, 0 deletions