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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:12:54 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:12:54 -0700 |
| commit | e410a925df8d37f386c97dc7cdd9a78347ce4700 (patch) | |
| tree | b4102987453b1303051dfeea61aa1a45c2e5e75f /src/arch/x86/isa/insts/control_transfer/xreturn.py | |
| parent | ced6cbcccf4540358093f060dad4d59ad6557d6a (diff) | |
| download | gem5-e410a925df8d37f386c97dc7cdd9a78347ce4700.tar.xz | |
X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
Diffstat (limited to 'src/arch/x86/isa/insts/control_transfer/xreturn.py')
| -rw-r--r-- | src/arch/x86/isa/insts/control_transfer/xreturn.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/insts/control_transfer/xreturn.py b/src/arch/x86/isa/insts/control_transfer/xreturn.py index 0000cd3c1..1efddf1d2 100644 --- a/src/arch/x86/isa/insts/control_transfer/xreturn.py +++ b/src/arch/x86/isa/insts/control_transfer/xreturn.py @@ -59,7 +59,7 @@ def macroop RET_NEAR # Make the default data size of rets 64 bits in 64 bit mode .adjust_env oszIn64Override - ld t1, ss, [0, t0, rsp] + ld t1, ss, [1, t0, rsp] addi rsp, rsp, dsz wripi t1, 0 }; @@ -70,7 +70,7 @@ def macroop RET_NEAR_I .adjust_env oszIn64Override limm t2, imm - ld t1, ss, [0, t0, rsp] + ld t1, ss, [1, t0, rsp] addi rsp, rsp, dsz add rsp, rsp, t2 wripi t1, 0 |