X86: Start implementing segmentation support.

Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.

--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9

1 files changed, 32 insertions, 32 deletions

diff --git a/src/arch/x86/isa/insts/data_transfer/conditional_move.py b/src/arch/x86/isa/insts/data_transfer/conditional_move.py
index 17f8841f2..1a60c5b61 100644
--- a/src/arch/x86/isa/insts/data_transfer/conditional_move.py
+++ b/src/arch/x86/isa/insts/data_transfer/conditional_move.py
@@ -61,14 +61,14 @@ def macroop CMOVZ_R_R
 
 def macroop CMOVZ_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(CZF,)
 };
 
 def macroop CMOVZ_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(CZF,)
 };
 
@@ -79,14 +79,14 @@ def macroop CMOVNZ_R_R
 
 def macroop CMOVNZ_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(nCZF,)
 };
 
 def macroop CMOVNZ_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(nCZF,)
 };
 
@@ -97,14 +97,14 @@ def macroop CMOVB_R_R
 
 def macroop CMOVB_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(CCF,)
 };
 
 def macroop CMOVB_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(CCF,)
 };
 
@@ -115,14 +115,14 @@ def macroop CMOVNB_R_R
 
 def macroop CMOVNB_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(nCCF,)
 };
 
 def macroop CMOVNB_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(nCCF,)
 };
 
@@ -133,14 +133,14 @@ def macroop CMOVBE_R_R
 
 def macroop CMOVBE_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(CCvZF,)
 };
 
 def macroop CMOVBE_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(CCvZF,)
 };
 
@@ -151,14 +151,14 @@ def macroop CMOVNBE_R_R
 
 def macroop CMOVNBE_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(nCCvZF,)
 };
 
 def macroop CMOVNBE_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(nCCvZF,)
 };
 
@@ -169,14 +169,14 @@ def macroop CMOVS_R_R
 
 def macroop CMOVS_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(CSF,)
 };
 
 def macroop CMOVS_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(CSF,)
 };
 
@@ -187,14 +187,14 @@ def macroop CMOVNS_R_R
 
 def macroop CMOVNS_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(nCSF,)
 };
 
 def macroop CMOVNS_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(nCSF,)
 };
 
@@ -205,14 +205,14 @@ def macroop CMOVP_R_R
 
 def macroop CMOVP_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(CPF,)
 };
 
 def macroop CMOVP_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(CPF,)
 };
 
@@ -223,14 +223,14 @@ def macroop CMOVNP_R_R
 
 def macroop CMOVNP_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, regm, flags=(nCPF,)
 };
 
 def macroop CMOVNP_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, regm, flags=(nCPF,)
 };
 
@@ -241,14 +241,14 @@ def macroop CMOVL_R_R
 
 def macroop CMOVL_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(CSxOF,)
 };
 
 def macroop CMOVL_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(CSxOF,)
 };
 
@@ -259,14 +259,14 @@ def macroop CMOVNL_R_R
 
 def macroop CMOVNL_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(nCSxOF,)
 };
 
 def macroop CMOVNL_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(nCSxOF,)
 };
 
@@ -277,14 +277,14 @@ def macroop CMOVLE_R_R
 
 def macroop CMOVLE_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(CSxOvZF,)
 };
 
 def macroop CMOVLE_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(CSxOvZF,)
 };
 
@@ -295,14 +295,14 @@ def macroop CMOVNLE_R_R
 
 def macroop CMOVNLE_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(nCSxOvZF,)
 };
 
 def macroop CMOVNLE_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(nCSxOvZF,)
 };
 
@@ -313,14 +313,14 @@ def macroop CMOVO_R_R
 
 def macroop CMOVO_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(COF,)
 };
 
 def macroop CMOVO_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(COF,)
 };
 
@@ -331,14 +331,14 @@ def macroop CMOVNO_R_R
 
 def macroop CMOVNO_R_M
 {
-    ld t1, ds, [scale, index, base], disp
+    ld t1, seg, sib, disp
     mov reg, reg, t1, flags=(nCOF,)
 };
 
 def macroop CMOVNO_R_P
 {
     rdip t7
-    ld t1, ds, [0, t0, t7], disp
+    ld t1, seg, riprel, disp
     mov reg, reg, t1, flags=(nCOF,)
 };
 '''