Merge more changes in from head.

--HG--
extra : convert_revision : 8f170f2754eccdb424a35b5b077225abcf6eee72

1 files changed, 81 insertions, 8 deletions

diff --git a/src/arch/x86/isa/insts/data_transfer/move.py b/src/arch/x86/isa/insts/data_transfer/move.py
index c85dd7cc4..bbc55e47c 100644
--- a/src/arch/x86/isa/insts/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/data_transfer/move.py
@@ -54,6 +54,11 @@
 # Authors: Gabe Black
 
 microcode = '''
+
+#
+# Regular moves
+#
+
 def macroop MOV_R_R {
     mov reg, reg, regm
 };
@@ -64,7 +69,7 @@ def macroop MOV_M_R {
 
 def macroop MOV_P_R {
     rdip t7
-    st reg, ds, [scale, index, base], disp
+    st reg, ds, [0, t0, t7], disp
 };
 
 def macroop MOV_R_M {
@@ -73,7 +78,7 @@ def macroop MOV_R_M {
 
 def macroop MOV_R_P {
     rdip t7
-    ld reg, ds, [scale, index, base], disp
+    ld reg, ds, [0, t0, t7], disp
 };
 
 def macroop MOV_R_I {
@@ -88,22 +93,90 @@ def macroop MOV_M_I {
 def macroop MOV_P_I {
     rdip t7
     limm t1, imm
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
+#
+# Sign extending moves
+#
+
 def macroop MOVSXD_R_R {
-    sext reg, regm, dsz
+    sext reg, regm, 32
 };
 
 def macroop MOVSXD_R_M {
-    ld t1, ds, [scale, index, base], disp
-    sext reg, t1, dsz
+    ld t1, ds, [scale, index, base], disp, dataSize=4
+    sext reg, t1, 32
 };
 
 def macroop MOVSXD_R_P {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
-    sext reg, t1, dsz
+    ld t1, ds, [0, t0, t7], disp, dataSize=4
+    sext reg, t1, 32
+};
+
+def macroop MOVSX_B_R_R {
+    sext reg, regm, 8
+};
+
+def macroop MOVSX_B_R_M {
+    ld reg, ds, [scale, index, base], disp, dataSize=1
+    sext reg, reg, 8
+};
+
+def macroop MOVSX_B_R_P {
+    rdip t7
+    ld reg, ds, [0, t0, t7], disp, dataSize=1
+    sext reg, reg, 8
+};
+
+def macroop MOVSX_W_R_R {
+    sext reg, regm, 16
+};
+
+def macroop MOVSX_W_R_M {
+    ld reg, ds, [scale, index, base], disp, dataSize=2
+    sext reg, reg, 16
+};
+
+def macroop MOVSX_W_R_P {
+    rdip t7
+    ld reg, ds, [0, t0, t7], disp, dataSize=2
+    sext reg, reg, 16
+};
+
+#
+# Zero extending moves
+#
+
+def macroop MOVZX_B_R_R {
+    zext reg, regm, 8
+};
+
+def macroop MOVZX_B_R_M {
+    ld t1, ds, [scale, index, base], disp, dataSize=1
+    zext reg, t1, 8
+};
+
+def macroop MOVZX_B_R_P {
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp, dataSize=1
+    zext reg, t1, 8
+};
+
+def macroop MOVZX_W_R_R {
+    zext reg, regm, 16
+};
+
+def macroop MOVZX_W_R_M {
+    ld t1, ds, [scale, index, base], disp, dataSize=2
+    zext reg, t1, 16
+};
+
+def macroop MOVZX_W_R_P {
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp, dataSize=2
+    zext reg, t1, 16
 };
 '''
 #let {{