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authorGabe Black <gblack@eecs.umich.edu>2007-06-19 14:18:25 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-06-19 14:18:25 +0000
commit6e286cddfaf6286f96e06c26266070f6fbbd7749 (patch)
treef318b62e376304d0b7f353a68794e4da160f5c8e /src/arch/x86/isa/insts/data_transfer/stack_operations.py
parent8caef7d25a6a150fa6369234bbdc8c14ef637df8 (diff)
downloadgem5-6e286cddfaf6286f96e06c26266070f6fbbd7749.tar.xz
Get rid of the immediate and displacement components of the EmulEnv struct and use them directly out of the instruction. The extra copies are conceptually realistic but are just innefficient as implemented. Also don't use the zeroeth microcode register for general storage since it's now the zero register, and implement a load and a store microops.
--HG-- extra : convert_revision : 0686296ca8b72940d961ecc6051063bfda1e932d
Diffstat (limited to 'src/arch/x86/isa/insts/data_transfer/stack_operations.py')
-rw-r--r--src/arch/x86/isa/insts/data_transfer/stack_operations.py10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
index b7ec0ec66..50b690354 100644
--- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
@@ -55,15 +55,21 @@
microcode = '''
def macroop POP_R {
+
+ # Make the default data size of pops 64 bits in 64 bit mode
.adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
- # There needs to be a load here to actually "pop" the data
+
+ ld "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
addi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
};
def macroop PUSH_R {
+
+ # Make the default data size of pops 64 bits in 64 bit mode
.adjust_env "if(machInst.mode.submode == SixtyFourBitMode && env.dataSize == 4) env.dataSize = 8\;"
+
subi "INTREG_RSP", "INTREG_RSP", "env.dataSize"
- # There needs to be a store here to actually "push" the data
+ st "env.reg", 2, [0, "NUM_INTREGS", "INTREG_RSP"]
};
'''
#let {{