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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:12:54 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:12:54 -0700 |
| commit | e410a925df8d37f386c97dc7cdd9a78347ce4700 (patch) | |
| tree | b4102987453b1303051dfeea61aa1a45c2e5e75f /src/arch/x86/isa/insts/data_transfer/xchg.py | |
| parent | ced6cbcccf4540358093f060dad4d59ad6557d6a (diff) | |
| download | gem5-e410a925df8d37f386c97dc7cdd9a78347ce4700.tar.xz | |
X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
Diffstat (limited to 'src/arch/x86/isa/insts/data_transfer/xchg.py')
| -rw-r--r-- | src/arch/x86/isa/insts/data_transfer/xchg.py | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/arch/x86/isa/insts/data_transfer/xchg.py b/src/arch/x86/isa/insts/data_transfer/xchg.py index 4f401deb7..9478c71fc 100644 --- a/src/arch/x86/isa/insts/data_transfer/xchg.py +++ b/src/arch/x86/isa/insts/data_transfer/xchg.py @@ -68,31 +68,31 @@ def macroop XCHG_R_R def macroop XCHG_R_M { - ld t1, ds, [scale, index, base], disp - st reg, ds, [scale, index, base], disp + ld t1, seg, sib, disp + st reg, seg, sib, disp mov reg, reg, t1 }; def macroop XCHG_R_P { rdip t7 - ld t1, ds, [0, t0, t7], disp - st reg, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp + st reg, seg, riprel, disp mov reg, reg, t1 }; def macroop XCHG_M_R { - ld t1, ds, [scale, index, base], disp - st reg, ds, [scale, index, base], disp + ld t1, seg, sib, disp + st reg, seg, sib, disp mov reg, reg, t1 }; def macroop XCHG_P_R { rdip t7 - ld t1, ds, [0, t0, t7], disp - st reg, ds, [0, t0, t7], disp + ld t1, seg, riprel, disp + st reg, seg, riprel, disp mov reg, reg, t1 }; ''' |