x86: Add microop for fence

This patch adds a new microop for memory barrier. The microop itself does
nothing, but since it is marked as a memory barrier, the O3 CPU should flush
all the pending loads and stores before the fence to the memory system.

1 files changed, 8 insertions, 0 deletions

diff --git a/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py
index f27cd7008..515082d64 100644
--- a/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py
+++ b/src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py
@@ -58,17 +58,21 @@ def macroop INC_P
 
 def macroop INC_LOCKED_M
 {
+    mfence
     ldstl t1, seg, sib, disp
     addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop INC_LOCKED_P
 {
     rdip t7
+    mfence
     ldstl t1, seg, riprel, disp
     addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
     stul t1, seg, riprel, disp
+    mfence
 };
 
 def macroop DEC_R
@@ -93,16 +97,20 @@ def macroop DEC_P
 
 def macroop DEC_LOCKED_M
 {
+    mfence
     ldstl t1, seg, sib, disp
     subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
     stul t1, seg, sib, disp
+    mfence
 };
 
 def macroop DEC_LOCKED_P
 {
     rdip t7
+    mfence
     ldstl t1, seg, riprel, disp
     subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
     stul t1, seg, riprel, disp
+    mfence
 };
 '''