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author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 04:56:36 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 04:56:36 -0700 |
commit | b493906eb9d7674d8ae1700d07168303ec56cf02 (patch) | |
tree | b9455feedefd59e34a2add88107bfcfb7b5926c2 /src/arch/x86/isa/insts/general_purpose/compare_and_test | |
parent | 985d959ea64dbfab142c2cb338c88641e2bcfc96 (diff) | |
download | gem5-b493906eb9d7674d8ae1700d07168303ec56cf02.tar.xz |
X86: Implement a locking version of BTS.
Diffstat (limited to 'src/arch/x86/isa/insts/general_purpose/compare_and_test')
-rw-r--r-- | src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py index e06add896..bc222300d 100644 --- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py @@ -274,6 +274,27 @@ def macroop BTS_P_I { st t1, seg, riprel, disp }; +def macroop BTS_LOCKED_M_I { + limm t1, imm, dataSize=asz + limm t4, 1 + roli t4, t4, imm + ldstl t1, seg, sib, disp + sexti t0, t1, imm, flags=(CF,) + or t1, t1, t4 + stul t1, seg, sib, disp +}; + +def macroop BTS_LOCKED_P_I { + rdip t7, dataSize=asz + limm t1, imm, dataSize=asz + limm t4, 1 + roli t4, t4, imm + ldstl t1, seg, riprel, disp + sexti t0, t1, imm, flags=(CF,) + or t1, t1, t4 + stul t1, seg, riprel, disp +}; + def macroop BTS_R_R { sext t0, reg, regm, flags=(CF,) limm t1, 1 @@ -305,4 +326,29 @@ def macroop BTS_P_R { or t1, t1, t4 st t1, seg, [1, t3, t7], disp }; + +def macroop BTS_LOCKED_M_R { + srai t2, reg, 3, dataSize=asz + srai t3, t2, ldsz, dataSize=asz + lea t3, flatseg, [dsz, t3, base], dataSize=asz + limm t4, 1 + rol t4, t4, reg + ldstl t1, seg, [scale, index, t3], disp + sext t0, t1, reg, flags=(CF,) + or t1, t1, t4 + stul t1, seg, [scale, index, t3], disp +}; + +def macroop BTS_LOCKED_P_R { + rdip t7, dataSize=asz + srai t2, reg, 3, dataSize=asz + srai t3, t2, ldsz, dataSize=asz + lea t3, flatseg, [dsz, t3, base], dataSize=asz + limm t4, 1 + rol t4, t4, reg + ldstl t1, seg, [1, t3, t7], disp + sext t0, t1, reg, flags=(CF,) + or t1, t1, t4 + stul t1, seg, [1, t3, t7], disp +}; ''' |