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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-16 09:27:56 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-16 09:27:56 -0700 |
| commit | 80c834ccac0b92cccd9756d4a2ec4cd4b46b6711 (patch) | |
| tree | 151624c71a962c03f5d916f1bd0e516610d4c3ba /src/arch/x86/isa/insts/general_purpose/compare_and_test | |
| parent | 3f9b0cc5ca126950fcce5a9b5ebf2f485ee812f2 (diff) | |
| download | gem5-80c834ccac0b92cccd9756d4a2ec4cd4b46b6711.tar.xz | |
X86: Fix a number of places where the wrong form of a microop was used.
Diffstat (limited to 'src/arch/x86/isa/insts/general_purpose/compare_and_test')
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py index 22364e038..da10d8478 100644 --- a/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py +++ b/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_scan.py @@ -84,7 +84,7 @@ microcode = ''' def macroop BSR_R_R { # Determine if the input was zero, and also move it to a temp reg. - movi t1, t1, t0, dataSize=8 + mov t1, t1, t0, dataSize=8 and t1, regm, regm, flags=(ZF,) br label("end"), flags=(CZF,) @@ -132,7 +132,7 @@ end: def macroop BSR_R_M { - movi t1, t1, t0, dataSize=8 + mov t1, t1, t0, dataSize=8 ld t1, seg, sib, disp # Determine if the input was zero, and also move it to a temp reg. @@ -184,7 +184,7 @@ end: def macroop BSR_R_P { rdip t7 - movi t1, t1, t0, dataSize=8 + mov t1, t1, t0, dataSize=8 ld t1, seg, riprel, disp # Determine if the input was zero, and also move it to a temp reg. |