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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:33:57 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:33:57 -0500 |
| commit | fba40864aab3015009efe4ade7599c07bc28ab1a (patch) | |
| tree | 0bd79a6e1bf9bd733c3b70376f13f8a825946a68 /src/arch/x86/isa/insts/general_purpose/control_transfer/call.py | |
| parent | 5b49c3d255eb82089496f8a77d6ab50004b5a2c2 (diff) | |
| download | gem5-fba40864aab3015009efe4ade7599c07bc28ab1a.tar.xz | |
x86: add op class for int and fp microops in isa description
Currently all the integer microops are marked as IntAluOp and the floating
point microops are marked as FloatAddOp. This patch adds support for marking
different microops differently. Now IntMultOp, IntDivOp, FloatDivOp,
FloatMultOp, FloatCvtOp, FloatSqrtOp classes will be used as well. This will
help in providing different latencies for different op class.
Diffstat (limited to 'src/arch/x86/isa/insts/general_purpose/control_transfer/call.py')
0 files changed, 0 insertions, 0 deletions