X86: Put ldst into the microcode (the earlier changeset didn't really).

Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.

--HG--
extra : convert_revision : 7c6050cb4798d287fe7d3cc4bb8c20dfa40ad2be

2 files changed, 14 insertions, 8 deletions

diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
index 9e6807039..5fb2b2172 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/stack_operations.py
@@ -67,6 +67,7 @@ def macroop POP_M {
     .adjust_env oszIn64Override
 
     ld t1, ss, [1, t0, rsp]
+    # Check stack address
     addi rsp, rsp, dsz
     st t1, seg, sib, disp
 };
@@ -77,6 +78,7 @@ def macroop POP_P {
 
     rdip t7
     ld t1, ss, [1, t0, rsp]
+    # Check stack address
     addi rsp, rsp, dsz
     st t1, seg, riprel, disp
 };
@@ -96,8 +98,8 @@ def macroop PUSH_I {
     .adjust_env oszIn64Override
 
     limm t1, imm
+    st t1, ss, [1, t0, rsp], "-env.dataSize"
     subi rsp, rsp, dsz
-    st t1, ss, [1, t0, rsp]
 };
 
 def macroop PUSH_M {
@@ -105,8 +107,8 @@ def macroop PUSH_M {
     .adjust_env oszIn64Override
 
     ld t1, seg, sib, disp
+    st t1, ss, [1, t0, rsp], "-env.dataSize"
     subi rsp, rsp, dsz
-    st t1, ss, [1, t0, rsp]
 };
 
 def macroop PUSH_P {
@@ -115,11 +117,13 @@ def macroop PUSH_P {
 
     rdip t7
     ld t1, seg, riprel, disp
+    # Check stack address
     subi rsp, rsp, dsz
     st t1, ss, [1, t0, rsp]
 };
 
 def macroop PUSHA {
+    # Check all the stack addresses.
     st rax, ss, [1, t0, rsp], "-0 * env.dataSize"
     st rcx, ss, [1, t0, rsp], "-1 * env.dataSize"
     st rdx, ss, [1, t0, rsp], "-2 * env.dataSize"
@@ -132,6 +136,7 @@ def macroop PUSHA {
 };
 
 def macroop POPA {
+    # Check all the stack addresses.
     ld rdi, ss, [1, t0, rsp], "0 * env.dataSize"
     ld rsi, ss, [1, t0, rsp], "1 * env.dataSize"
     ld rbp, ss, [1, t0, rsp], "2 * env.dataSize"
@@ -146,8 +151,9 @@ def macroop LEAVE {
     # Make the default data size of pops 64 bits in 64 bit mode
     .adjust_env oszIn64Override
 
-    mov rsp, rsp, rbp
-    ld rbp, ss, [1, t0, rsp]
+    mov t1, t1, rbp
+    ld rbp, ss, [1, t0, t1]
+    mov rsp, rsp, t1
     addi rsp, rsp, dsz
 };
 '''
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
index 9478c71fc..3f243f5d8 100644
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/xchg.py
@@ -68,7 +68,7 @@ def macroop XCHG_R_R
 
 def macroop XCHG_R_M
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     st reg, seg, sib, disp
     mov reg, reg, t1
 };
@@ -76,14 +76,14 @@ def macroop XCHG_R_M
 def macroop XCHG_R_P
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     st reg, seg, riprel, disp
     mov reg, reg, t1
 };
 
 def macroop XCHG_M_R
 {
-    ld t1, seg, sib, disp
+    ldst t1, seg, sib, disp
     st reg, seg, sib, disp
     mov reg, reg, t1
 };
@@ -91,7 +91,7 @@ def macroop XCHG_M_R
 def macroop XCHG_P_R
 {
     rdip t7
-    ld t1, seg, riprel, disp
+    ldst t1, seg, riprel, disp
     st reg, seg, riprel, disp
     mov reg, reg, t1
 };