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author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 03:47:59 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 03:47:59 -0700 |
commit | 3eed59768c39c6faeb1be0f3bc0bb283656c1f90 (patch) | |
tree | c0e9204f5264720a0e82d0863ee188be071c8a90 /src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py | |
parent | 8761057c7884103a8614ae174fa7e63c9291ba3d (diff) | |
download | gem5-3eed59768c39c6faeb1be0f3bc0bb283656c1f90.tar.xz |
X86: Explicitly use the right width in a few places that need a 64 bit value.
Diffstat (limited to 'src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py')
-rw-r--r-- | src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py b/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py index e151dc61d..cfd90638b 100644 --- a/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py +++ b/src/arch/x86/isa/insts/general_purpose/flags/set_and_clear.py @@ -56,14 +56,14 @@ microcode = ''' def macroop CLD { ruflags t1 - limm t2, "~((uint64_t)DFBit)" + limm t2, "~((uint64_t)DFBit)", dataSize=8 and t1, t1, t2 wruflags t1, t0 }; def macroop STD { ruflags t1 - limm t2, "DFBit" + limm t2, "DFBit", dataSize=8 or t1, t1, t2 wruflags t1, t0 }; @@ -87,14 +87,14 @@ def macroop CMC { def macroop STI { rflags t1 - limm t2, "IFBit" + limm t2, "IFBit", dataSize=8 or t1, t1, t2 wrflags t1, t0 }; def macroop CLI { rflags t1 - limm t2, "~IFBit" + limm t2, "~IFBit", dataSize=8 and t1, t1, t2 wrflags t1, t0 }; |