X86: Make instructions that use intseg preserve all 8 bytes of their addresses.

1 files changed, 4 insertions, 4 deletions

diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
index 924bfcb6e..4e3c9b316 100644
--- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
@@ -85,22 +85,22 @@ microcode = '''
     def macroop IN_R_I {
         .adjust_imm trimImm(8)
         limm t1, imm, dataSize=asz
-        ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
+        ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8
     };
 
     def macroop IN_R_R {
         zexti t2, regm, 15, dataSize=8
-        ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
+        ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
     };
 
     def macroop OUT_I_R {
         .adjust_imm trimImm(8)
         limm t1, imm, dataSize=8
-        st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4
+        st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8
     };
 
     def macroop OUT_R_R {
         zexti t2, reg, 15, dataSize=8
-        st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4
+        st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8
     };
 '''