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author | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:47:25 -0400 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:47:25 -0400 |
commit | a8e3001df85bc1e435a8abe77141ba0f6c9b7f9e (patch) | |
tree | 6b74fae6fb0b7ebd79e24289bdea69e035ae4b69 /src/arch/x86/isa/insts/general_purpose/input_output/general_io.py | |
parent | b3e55339f90dbf7f719e8f8348356e1ad03d74bb (diff) | |
download | gem5-a8e3001df85bc1e435a8abe77141ba0f6c9b7f9e.tar.xz |
X86: Bypass unaligned access support for register addressed MSRs.
Diffstat (limited to 'src/arch/x86/isa/insts/general_purpose/input_output/general_io.py')
-rw-r--r-- | src/arch/x86/isa/insts/general_purpose/input_output/general_io.py | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py index 1986a322e..aba318d73 100644 --- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py @@ -84,25 +84,23 @@ microcode = ''' def macroop IN_R_I { .adjust_imm trimImm(8) - limm t1, "IntAddrPrefixIO", dataSize=8 - ld reg, intseg, [1, t1, t0], imm, addressSize=8 + limm t1, imm, dataSize=asz + ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4 }; def macroop IN_R_R { - limm t1, "IntAddrPrefixIO", dataSize=8 zexti t2, regm, 15, dataSize=2 - ld reg, intseg, [1, t1, t2], addressSize=8 + ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4 }; def macroop OUT_I_R { .adjust_imm trimImm(8) - limm t1, "IntAddrPrefixIO", dataSize=8 - st reg, intseg, [1, t1, t0], imm, addressSize=8 + limm t1, imm, dataSize=8 + st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=4 }; def macroop OUT_R_R { - limm t1, "IntAddrPrefixIO", dataSize=8 zexti t2, reg, 15, dataSize=2 - st regm, intseg, [1, t1, t2], addressSize=8 + st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=4 }; ''' |