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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:45 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-11-12 14:38:45 -0800 |
| commit | f9ddb894dd92d6cc5601d65a3c58dc5dd73f7ac7 (patch) | |
| tree | decee5793bb85d01031164d6df674d04d9c36c36 /src/arch/x86/isa/insts/general_purpose/input_output/general_io.py | |
| parent | 6d4ba8de34e4427a0488e6bc0a9f5b9ec5b1a265 (diff) | |
| download | gem5-f9ddb894dd92d6cc5601d65a3c58dc5dd73f7ac7.tar.xz | |
X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.
--HG--
extra : convert_revision : 08bd7b4ff183038c016612d04ac73b20a255d141
Diffstat (limited to 'src/arch/x86/isa/insts/general_purpose/input_output/general_io.py')
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/input_output/general_io.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py index c01a11035..75a361eb7 100644 --- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py @@ -62,7 +62,7 @@ microcode = ''' def macroop IN_R_R { limm t1, "IntAddrPrefixIO" - zext t2, regm, 16, dataSize=2 + zexti t2, regm, 15, dataSize=2 ld reg, intseg, [1, t1, t2], addressSize=8 }; @@ -74,7 +74,7 @@ microcode = ''' def macroop OUT_R_R { limm t1, "IntAddrPrefixIO" - zext t2, reg, 16, dataSize=2 + zexti t2, reg, 15, dataSize=2 st regm, intseg, [1, t1, t2], addressSize=8 }; ''' |