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| author | Gabe Black <gabeblack@google.com> | 2018-03-12 17:06:14 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-03-14 20:06:47 +0000 |
| commit | 0f425ad5d590f670efac118b03e591579da21e84 (patch) | |
| tree | d489726f84324dcc07128551d69fcf866f47e5ec /src/arch/x86/isa/insts/general_purpose | |
| parent | 9f8491ecbfb80696b62a5a878fe40f81a8a0d35c (diff) | |
| download | gem5-0f425ad5d590f670efac118b03e591579da21e84.tar.xz | |
x86: Replace the .serializing directive with .serialize_(before|after).
This makes it explicit which type of serialization you want, and also
makes it possible to make a macroop serialize before. The old
serializing directive was renamed .serialize_after in the microcode
assembler, and throughout the microcode implementation, and its
behavior is unchanged. More specifically, it still marks the last
microop within the macroop as IsSerializing and IsSerializeAfter.
The new .serialize_before directive does something similar and marks
the first microop as IsSerializing and IsSerializeBefore.
Change-Id: Ia53466c734c651c65400809de7ef903c4a6c3e7e
Reviewed-on: https://gem5-review.googlesource.com/9041
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/x86/isa/insts/general_purpose')
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py | 4 | ||||
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/data_transfer/move.py | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py index 70cbd1075..004708080 100644 --- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py @@ -37,12 +37,12 @@ microcode = ''' def macroop IRET_REAL { - .serializing + .serialize_after panic "Real mode iret isn't implemented!" }; def macroop IRET_PROT { - .serializing + .serialize_after .adjust_env oszIn64Override # Check for a nested task. This isn't supported at the moment. diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py index 75a20ffbd..13d2f18e0 100644 --- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py +++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py @@ -174,19 +174,19 @@ def macroop MOVZX_W_R_P { }; def macroop MOV_C_R { - .serializing + .serialize_after .adjust_env maxOsz wrcr reg, regm }; def macroop MOV_R_C { - .serializing + .serialize_after .adjust_env maxOsz rdcr reg, regm }; def macroop MOV_D_R { - .serializing + .serialize_after .adjust_env maxOsz wrdr reg, regm }; |