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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-01-25 20:31:17 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-01-25 20:31:17 -0800 |
| commit | 0449fb2b7a51f911d9814b79250047fa8f083829 (patch) | |
| tree | 37553a23c44b0cfa716d019464d2e1ab48e988e6 /src/arch/x86/isa/insts/general_purpose | |
| parent | 389fbfdab19332ad191e9abed1c12a673fb7eda9 (diff) | |
| download | gem5-0449fb2b7a51f911d9814b79250047fa8f083829.tar.xz | |
X86: Fix a bug in the iret microcode.
Diffstat (limited to 'src/arch/x86/isa/insts/general_purpose')
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py index 57bc13698..1f14eb95c 100644 --- a/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py +++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py @@ -75,6 +75,8 @@ def macroop IRET_PROT { ld t2, ss, [1, t0, rsp], "1 * env.stackSize", dataSize=ssz ld t3, ss, [1, t0, rsp], "2 * env.stackSize", dataSize=ssz + # Read the handy m5 register for use later + rdm5reg t4 ### @@ -89,7 +91,6 @@ def macroop IRET_PROT { br label("protToVirtFallThrough"), flags=(nCECF,) #CPL=0 - rdm5reg t4 andi t0, t4, 0x30, flags=(EZF,) br label("protToVirtFallThrough"), flags=(nCEZF,) |