diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 02:59:39 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 02:59:39 -0700 |
| commit | 88041f75c44680f07e707339afd8fb81526fd256 (patch) | |
| tree | c2b9602eb2b73d471109314448faf74afb958ef2 /src/arch/x86/isa/insts/general_purpose | |
| parent | 029d360db215ae081a2cba0b5552eaf77f509b20 (diff) | |
| download | gem5-88041f75c44680f07e707339afd8fb81526fd256.tar.xz | |
X86: Set the flags on a rotate right instruction.
Diffstat (limited to 'src/arch/x86/isa/insts/general_purpose')
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py index 41d68106a..118afbf9f 100644 --- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py +++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py @@ -116,13 +116,13 @@ def macroop ROL_P_R def macroop ROR_R_I { - rori reg, reg, imm + rori reg, reg, imm, flags=(OF,CF) }; def macroop ROR_M_I { ldst t1, seg, sib, disp - rori t1, t1, imm + rori t1, t1, imm, flags=(OF,CF) st t1, seg, sib, disp }; @@ -130,19 +130,19 @@ def macroop ROR_P_I { rdip t7 ldst t1, seg, riprel, disp - rori t1, t1, imm + rori t1, t1, imm, flags=(OF,CF) st t1, seg, riprel, disp }; def macroop ROR_1_R { - rori reg, reg, 1 + rori reg, reg, 1, flags=(OF,CF) }; def macroop ROR_1_M { ldst t1, seg, sib, disp - rori t1, t1, 1 + rori t1, t1, 1, flags=(OF,CF) st t1, seg, sib, disp }; @@ -150,19 +150,19 @@ def macroop ROR_1_P { rdip t7 ldst t1, seg, riprel, disp - rori t1, t1, 1 + rori t1, t1, 1, flags=(OF,CF) st t1, seg, riprel, disp }; def macroop ROR_R_R { - ror reg, reg, regm + ror reg, reg, regm, flags=(OF,CF) }; def macroop ROR_M_R { ldst t1, seg, sib, disp - ror t1, t1, reg + ror t1, t1, reg, flags=(OF,CF) st t1, seg, sib, disp }; @@ -170,7 +170,7 @@ def macroop ROR_P_R { rdip t7 ldst t1, seg, riprel, disp - ror t1, t1, reg + ror t1, t1, reg, flags=(OF,CF) st t1, seg, riprel, disp }; |