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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 02:58:20 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 02:58:20 -0700 |
| commit | 99adfd9dae5c846ebc2493fee7346aef96c96ec5 (patch) | |
| tree | b179cf06083e7712cf088f52f34164f13b83d802 /src/arch/x86/isa/insts/general_purpose | |
| parent | c087b60af34abb2b496d2308327071c45c1a9a04 (diff) | |
| download | gem5-99adfd9dae5c846ebc2493fee7346aef96c96ec5.tar.xz | |
X86: Actually set the flags on a rotate left instruction.
Diffstat (limited to 'src/arch/x86/isa/insts/general_purpose')
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py index b5ae9560e..41d68106a 100644 --- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py +++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py @@ -56,13 +56,13 @@ microcode = ''' def macroop ROL_R_I { - roli reg, reg, imm + roli reg, reg, imm, flags=(OF,CF) }; def macroop ROL_M_I { ldst t1, seg, sib, disp - roli t1, t1, imm + roli t1, t1, imm, flags=(OF,CF) st t1, seg, sib, disp }; @@ -70,19 +70,19 @@ def macroop ROL_P_I { rdip t7 ldst t1, seg, riprel, disp - roli t1, t1, imm + roli t1, t1, imm, flags=(OF,CF) st t1, seg, riprel, disp }; def macroop ROL_1_R { - roli reg, reg, 1 + roli reg, reg, 1, flags=(OF,CF) }; def macroop ROL_1_M { ldst t1, seg, sib, disp - roli t1, t1, 1 + roli t1, t1, 1, flags=(OF,CF) st t1, seg, sib, disp }; @@ -90,19 +90,19 @@ def macroop ROL_1_P { rdip t7 ldst t1, seg, riprel, disp - roli t1, t1, 1 + roli t1, t1, 1, flags=(OF,CF) st t1, seg, riprel, disp }; def macroop ROL_R_R { - rol reg, reg, regm + rol reg, reg, regm, flags=(OF,CF) }; def macroop ROL_M_R { ldst t1, seg, sib, disp - rol t1, t1, reg + rol t1, t1, reg, flags=(OF,CF) st t1, seg, sib, disp }; @@ -110,7 +110,7 @@ def macroop ROL_P_R { rdip t7 ldst t1, seg, riprel, disp - rol t1, t1, reg + rol t1, t1, reg, flags=(OF,CF) st t1, seg, riprel, disp }; |