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author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:12:54 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-04 20:12:54 -0700 |
commit | e410a925df8d37f386c97dc7cdd9a78347ce4700 (patch) | |
tree | b4102987453b1303051dfeea61aa1a45c2e5e75f /src/arch/x86/isa/insts/load_effective_address.py | |
parent | ced6cbcccf4540358093f060dad4d59ad6557d6a (diff) | |
download | gem5-e410a925df8d37f386c97dc7cdd9a78347ce4700.tar.xz |
X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
Diffstat (limited to 'src/arch/x86/isa/insts/load_effective_address.py')
-rw-r--r-- | src/arch/x86/isa/insts/load_effective_address.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/insts/load_effective_address.py b/src/arch/x86/isa/insts/load_effective_address.py index fc8b17629..0c4e0f7df 100644 --- a/src/arch/x86/isa/insts/load_effective_address.py +++ b/src/arch/x86/isa/insts/load_effective_address.py @@ -55,11 +55,11 @@ microcode = ''' def macroop LEA_R_M { - lea reg, ds, [scale, index, base], disp + lea reg, seg, sib, disp }; def macroop LEA_R_P { rdip t7 - lea reg, ds, [0, t0, t7], disp + lea reg, seg, riprel, disp }; ''' |