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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-07-22 08:10:59 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-07-22 08:10:59 -0700 |
| commit | d5c74657c986a1c6730393d76da6d8859ae7fca4 (patch) | |
| tree | 9de36c35735432220f010b98a25b0f380d13ef6a /src/arch/x86/isa/insts/logical.py | |
| parent | 1c2d5f5e64387527efe495a59f6946e7b539a543 (diff) | |
| parent | 03730edc45e2e00bdec58dabc84e94c632634a1a (diff) | |
| download | gem5-d5c74657c986a1c6730393d76da6d8859ae7fca4.tar.xz | |
Merge more changes in from head.
--HG--
extra : convert_revision : 8f170f2754eccdb424a35b5b077225abcf6eee72
Diffstat (limited to 'src/arch/x86/isa/insts/logical.py')
| -rw-r--r-- | src/arch/x86/isa/insts/logical.py | 106 |
1 files changed, 106 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py index 2fd369d60..f99638cac 100644 --- a/src/arch/x86/isa/insts/logical.py +++ b/src/arch/x86/isa/insts/logical.py @@ -54,6 +54,62 @@ # Authors: Gabe Black microcode = ''' +def macroop OR_R_R +{ + or reg, reg, regm +}; + +def macroop OR_M_I +{ + limm t2, imm + ld t1, ds, [scale, index, base], disp + or t1, t1, t2 + st t1, ds, [scale, index, base], disp +}; + +def macroop OR_P_I +{ + limm t2, imm + rdip t7 + ld t1, ds, [0, t0, t7], disp + or t1, t1, t2 + st t1, ds, [0, t0, t7], disp +}; + +def macroop OR_M_R +{ + ld t1, ds, [scale, index, base], disp + or t1, t1, reg + st t1, ds, [scale, index, base], disp +}; + +def macroop OR_P_R +{ + rdip t7 + ld t1, ds, [0, t0, t7], disp + or t1, t1, reg + st t1, ds, [0, t0, t7], disp +}; + +def macroop OR_R_M +{ + ld t1, ds, [scale, index, base], disp + or reg, reg, t1 +}; + +def macroop OR_R_P +{ + rdip t7 + ld t1, ds, [0, t0, t7], disp + or reg, reg, t1 +}; + +def macroop OR_R_I +{ + limm t1, imm + or reg, reg, t1 +}; + def macroop XOR_R_R { xor reg, reg, regm @@ -65,6 +121,23 @@ def macroop XOR_R_I xor reg, reg, t1 }; +def macroop XOR_M_I +{ + limm t2, imm + ld t1, ds, [scale, index, base], disp + xor t1, t1, t2 + st t1, ds, [scale, index, base], disp +}; + +def macroop XOR_P_I +{ + limm t2, imm + rdip t7 + ld t1, ds, [scale, index, base], disp + xor t1, t1, t2 + st t1, ds, [scale, index, base], disp +}; + def macroop XOR_M_R { ld t1, ds, [scale, index, base], disp @@ -93,6 +166,24 @@ def macroop XOR_R_P xor reg, reg, t1 }; +def macroop AND_R_R +{ + and reg, reg, regm +}; + +def macroop AND_R_M +{ + ld t1, ds, [scale, index, base], disp + and reg, reg, t1 +}; + +def macroop AND_R_P +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + and reg, reg, t1 +}; + def macroop AND_R_I { limm t1, imm @@ -115,6 +206,21 @@ def macroop AND_P_I and t2, t2, t1 st t2, ds, [scale, index, base], disp }; + +def macroop AND_M_R +{ + ld t1, ds, [scale, index, base], disp + and t1, t1, reg + st t1, ds, [scale, index, base], disp +}; + +def macroop AND_P_R +{ + rdip t7 + ld t1, ds, [scale, index, base], disp + and t1, t1, reg + st t1, ds, [scale, index, base], disp +}; ''' #let {{ #microcodeString = ''' |