Merge from head.

--HG--
extra : convert_revision : af16bc685ea28e44b8120f16b72f60a21d68c1e2

1 files changed, 24 insertions, 24 deletions

diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py
index bbc15f8fa..81a4730de 100644
--- a/src/arch/x86/isa/insts/logical.py
+++ b/src/arch/x86/isa/insts/logical.py
@@ -56,14 +56,14 @@
 microcode = '''
 def macroop OR_R_R
 {
-    or reg, reg, regm
+    or reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop OR_M_I
 {
     limm t2, imm
     ld t1, ds, [scale, index, base], disp
-    or t1, t1, t2
+    or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -72,14 +72,14 @@ def macroop OR_P_I
     limm t2, imm
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    or t1, t1, t2
+    or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop OR_M_R
 {
     ld t1, ds, [scale, index, base], disp
-    or t1, t1, reg
+    or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -87,45 +87,45 @@ def macroop OR_P_R
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    or t1, t1, reg
+    or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop OR_R_M
 {
     ld t1, ds, [scale, index, base], disp
-    or reg, reg, t1
+    or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop OR_R_P
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    or reg, reg, t1
+    or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop OR_R_I
 {
     limm t1, imm
-    or reg, reg, t1
+    or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop XOR_R_R
 {
-    xor reg, reg, regm
+    xor reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop XOR_R_I
 {
     limm t1, imm
-    xor reg, reg, t1
+    xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop XOR_M_I
 {
     limm t2, imm
     ld t1, ds, [scale, index, base], disp
-    xor t1, t1, t2
+    xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -134,14 +134,14 @@ def macroop XOR_P_I
     limm t2, imm
     rdip t7
     ld t1, ds, [scale, index, base], disp
-    xor t1, t1, t2
+    xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
 def macroop XOR_M_R
 {
     ld t1, ds, [scale, index, base], disp
-    xor t1, t1, reg
+    xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -149,52 +149,52 @@ def macroop XOR_P_R
 {
     rdip t7
     ld t1, ds, [scale, index, base], disp
-    xor t1, t1, reg
+    xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
 def macroop XOR_R_M
 {
     ld t1, ds, [scale, index, base], disp
-    xor reg, reg, t1
+    xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop XOR_R_P
 {
     rdip t7
     ld t1, ds, [scale, index, base], disp
-    xor reg, reg, t1
+    xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop AND_R_R
 {
-    and reg, reg, regm
+    and reg, reg, regm, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop AND_R_M
 {
     ld t1, ds, [scale, index, base], disp
-    and reg, reg, t1
+    and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop AND_R_P
 {
     rdip t7
     ld t1, ds, [scale, index, base], disp
-    and reg, reg, t1
+    and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop AND_R_I
 {
     limm t1, imm
-    and reg, reg, t1
+    and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
 };
 
 def macroop AND_M_I
 {
     ld t2, ds, [scale, index, base], disp
     limm t1, imm
-    and t2, t2, t1
+    and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
     st t2, ds, [scale, index, base], disp
 };
 
@@ -203,14 +203,14 @@ def macroop AND_P_I
     rdip t7
     ld t2, ds, [scale, index, base], disp
     limm t1, imm
-    and t2, t2, t1
+    and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
     st t2, ds, [scale, index, base], disp
 };
 
 def macroop AND_M_R
 {
     ld t1, ds, [scale, index, base], disp
-    and t1, t1, reg
+    and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };
 
@@ -218,7 +218,7 @@ def macroop AND_P_R
 {
     rdip t7
     ld t1, ds, [scale, index, base], disp
-    and t1, t1, reg
+    and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
     st t1, ds, [scale, index, base], disp
 };