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authorGabe Black <gblack@eecs.umich.edu>2009-08-17 20:25:14 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-08-17 20:25:14 -0700
commit179fd4e536e12cbd1baeefbd9d8ac0557f899003 (patch)
treedbbbf29c7eb13e12836e450552d5536adaf47899 /src/arch/x86/isa/insts/simd128
parentb315c3effc89127017c34b55908e7e63adca3f11 (diff)
downloadgem5-179fd4e536e12cbd1baeefbd9d8ac0557f899003.tar.xz
X86: Implement LDMXCSR.
Diffstat (limited to 'src/arch/x86/isa/insts/simd128')
-rw-r--r--src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
index 831a266c7..2481b744f 100644
--- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
+++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_control_and_status.py
@@ -64,5 +64,15 @@ def macroop STMXCSR_P {
rdip t7
st t1, seg, riprel, disp
};
-# LDMXCSR
+
+def macroop LDMXCSR_M {
+ ld t1, seg, sib, disp
+ wrval "InstRegIndex(MISCREG_MXCSR)", t1
+};
+
+def macroop LDMXCSR_P {
+ rdip t7
+ ld t1, seg, riprel, disp
+ wrval "InstRegIndex(MISCREG_MXCSR)", t1
+};
'''