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authorNikos Nikoleris <nikos.nikoleris@gmail.com>2015-07-04 10:43:47 -0500
committerNikos Nikoleris <nikos.nikoleris@gmail.com>2015-07-04 10:43:47 -0500
commit67925a833445a8b2ddce0fae4c86677ce0f4298d (patch)
treeab50d5047d928846e502719401df0b7d1df96c06 /src/arch/x86/isa/insts/simd128
parent64af6dafb1edd1287185d3e15c9071836e02b578 (diff)
downloadgem5-67925a833445a8b2ddce0fae4c86677ce0f4298d.tar.xz
x86: Adjust the size of the values written to the x87 misc registers
All x87 misc registers are implemented in an array of 64 bit values but in real hardware the size of some of these registers is smaller. Previsouly all 64 bits where incorrectly set and then later read. To ensure correctness we mask the value in setMiscRegNoEffect to write only the valid bits. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/arch/x86/isa/insts/simd128')
-rw-r--r--src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
index 1017d519f..2b9ad756e 100644
--- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
+++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
@@ -122,9 +122,6 @@ fxrstorCommonTemplate = """
# FSW includes TOP when read
ld t1, seg, %(mode)s, "DISPLACEMENT + 2", dataSize=2
wrval fsw, t1
- srli t1, t1, 11, dataSize=2
- andi t1, t1, 0x7, dataSize=2
- wrval "InstRegIndex(MISCREG_X87_TOP)", t1
# FTW
ld t1, seg, %(mode)s, "DISPLACEMENT + 4", dataSize=1