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authorKorey Sewell <ksewell@umich.edu>2007-11-15 00:14:20 -0500
committerKorey Sewell <ksewell@umich.edu>2007-11-15 00:14:20 -0500
commit375ddf8d25c3d81a77bd5dd7b70f84a0dbe48fe8 (patch)
tree525cf56502718b69fb7f0e78162a8d5e63256489 /src/arch/x86/isa/insts/system/msrs.py
parent2820a448e2bcb861d099b1256087004462b78895 (diff)
parent7c8e4ca3a3b66becbc3e4e7b5e106f5c44b09b6f (diff)
downloadgem5-375ddf8d25c3d81a77bd5dd7b70f84a0dbe48fe8.tar.xz
branch merge
--HG-- extra : convert_revision : 1c56f3c6f2c50d642d2de5ddde83a55234455cec
Diffstat (limited to 'src/arch/x86/isa/insts/system/msrs.py')
-rw-r--r--src/arch/x86/isa/insts/system/msrs.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py
index ea576510b..20b9b2a0b 100644
--- a/src/arch/x86/isa/insts/system/msrs.py
+++ b/src/arch/x86/isa/insts/system/msrs.py
@@ -54,7 +54,7 @@
# Authors: Gabe Black
microcode = '''
-def macroop WRMSR
+def macroop RDMSR
{
limm t1, "IntAddrPrefixMSR >> 3"
ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
@@ -63,7 +63,7 @@ def macroop WRMSR
mov rdx, rdx, t2, dataSize=4
};
-def macroop RDMSR
+def macroop WRMSR
{
limm t1, "IntAddrPrefixMSR >> 3"
mov t2, t2, rdx, dataSize=4