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| author | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:47:25 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2008-06-12 00:47:25 -0400 |
| commit | a8e3001df85bc1e435a8abe77141ba0f6c9b7f9e (patch) | |
| tree | 6b74fae6fb0b7ebd79e24289bdea69e035ae4b69 /src/arch/x86/isa/insts/system/msrs.py | |
| parent | b3e55339f90dbf7f719e8f8348356e1ad03d74bb (diff) | |
| download | gem5-a8e3001df85bc1e435a8abe77141ba0f6c9b7f9e.tar.xz | |
X86: Bypass unaligned access support for register addressed MSRs.
Diffstat (limited to 'src/arch/x86/isa/insts/system/msrs.py')
| -rw-r--r-- | src/arch/x86/isa/insts/system/msrs.py | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py index 461ed1054..f3c867398 100644 --- a/src/arch/x86/isa/insts/system/msrs.py +++ b/src/arch/x86/isa/insts/system/msrs.py @@ -84,8 +84,8 @@ microcode = ''' def macroop RDMSR { - limm t1, "IntAddrPrefixMSR >> 3" - ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4 + ld t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \ + dataSize=8, addressSize=4 mov rax, rax, t2, dataSize=4 srli t2, t2, 32, dataSize=8 mov rdx, rdx, t2, dataSize=4 @@ -93,11 +93,11 @@ def macroop RDMSR def macroop WRMSR { - limm t1, "IntAddrPrefixMSR >> 3" mov t2, t2, rax, dataSize=4 slli t3, rdx, 32, dataSize=8 or t2, t2, t3, dataSize=8 - st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4 + st t2, intseg, [8, rcx, t0], "IntAddrPrefixMSR << 3", \ + dataSize=8, addressSize=4 }; def macroop RDTSC |