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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-08-23 09:44:19 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-08-23 09:44:19 -0700 |
| commit | d43eb42d00a587405a512396c6524be95d5a6311 (patch) | |
| tree | c265195d521b0af13581def7ba507f64f137cf91 /src/arch/x86/isa/insts/system/msrs.py | |
| parent | 69fc2af00600ced942d81dba082d9780e5325c9e (diff) | |
| download | gem5-d43eb42d00a587405a512396c6524be95d5a6311.tar.xz | |
X86: Mark serializing macroops and regular instructions as such.
Diffstat (limited to 'src/arch/x86/isa/insts/system/msrs.py')
| -rw-r--r-- | src/arch/x86/isa/insts/system/msrs.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/system/msrs.py b/src/arch/x86/isa/insts/system/msrs.py index 95832442c..d0e2675de 100644 --- a/src/arch/x86/isa/insts/system/msrs.py +++ b/src/arch/x86/isa/insts/system/msrs.py @@ -50,6 +50,7 @@ def macroop RDMSR def macroop WRMSR { + .serializing mov t2, t2, rax, dataSize=4 slli t3, rdx, 32, dataSize=8 or t2, t2, t3, dataSize=8 |