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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 03:22:38 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-19 03:22:38 -0700 |
| commit | bdd55ec8b6eda4b46288d8f85a5a9fa603cd6ab4 (patch) | |
| tree | 7e3e589fb17df300bde7eea42cca14e614f8ea91 /src/arch/x86/isa/insts/system | |
| parent | d86cd1d2a02d2dd42e6b0f6e8bc8b8876c3d6152 (diff) | |
| download | gem5-bdd55ec8b6eda4b46288d8f85a5a9fa603cd6ab4.tar.xz | |
X86: Implement the save machine status word instruction (SMSW).
Diffstat (limited to 'src/arch/x86/isa/insts/system')
| -rw-r--r-- | src/arch/x86/isa/insts/system/control_registers.py | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/x86/isa/insts/system/control_registers.py b/src/arch/x86/isa/insts/system/control_registers.py index c09cdf6e8..82811bb07 100644 --- a/src/arch/x86/isa/insts/system/control_registers.py +++ b/src/arch/x86/isa/insts/system/control_registers.py @@ -68,4 +68,19 @@ def macroop LMSW_P { or t1, t1, t2, dataSize=8 wrcr 0, t1, dataSize=8 }; + +def macroop SMSW_R { + rdcr reg, 0 +}; + +def macroop SMSW_M { + rdcr t1, 0 + st t1, seg, sib, disp, dataSize=2 +}; + +def macroop SMSW_P { + rdcr t1, 0 + rdip t7, dataSize=asz + st t1, seg, riprel, disp, dataSize=2 +}; ''' |