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authorDavid Hashe <david.hashe@amd.com>2015-07-20 09:15:18 -0500
committerDavid Hashe <david.hashe@amd.com>2015-07-20 09:15:18 -0500
commita2d9aae3c3dae1ffdd62eb91d2318758772684dc (patch)
tree84a3cd2212175939cb6589547f89858d48e7bb55 /src/arch/x86/isa/insts/system
parent9560893f0d2e74d1c6c22fee501cd24d4f6e13d7 (diff)
downloadgem5-a2d9aae3c3dae1ffdd62eb91d2318758772684dc.tar.xz
x86: x86 instruction-implementation bug fixes
Added explicit data sizes and an opcode type for correct execution.
Diffstat (limited to 'src/arch/x86/isa/insts/system')
-rw-r--r--src/arch/x86/isa/insts/system/segmentation.py5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/x86/isa/insts/system/segmentation.py b/src/arch/x86/isa/insts/system/segmentation.py
index 53b6908ed..3c8648127 100644
--- a/src/arch/x86/isa/insts/system/segmentation.py
+++ b/src/arch/x86/isa/insts/system/segmentation.py
@@ -1,4 +1,5 @@
# Copyright (c) 2007 The Hewlett-Packard Development Company
+# Copyright (c) 2012-2013 AMD
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -78,7 +79,7 @@ def macroop LGDT_16_M
# Get the base
ld t2, seg, sib, 'adjustedDisp + 2', dataSize=4
zexti t2, t2, 23, dataSize=8
- wrbase tsg, t2
+ wrbase tsg, t2, dataSize=8
wrlimit tsg, t1
};
@@ -139,7 +140,7 @@ def macroop LIDT_16_M
# Get the base
ld t2, seg, sib, 'adjustedDisp + 2', dataSize=4
zexti t2, t2, 23, dataSize=8
- wrbase idtr, t2
+ wrbase idtr, t2, dataSize=8
wrlimit idtr, t1
};