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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 03:00:23 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-08-05 03:00:23 -0700 |
| commit | 4e4adcaaa82b8a308bb0752b47ec509fb382e975 (patch) | |
| tree | e2d792c86c82b5e4cf4d6794efb0ea0fc46f398d /src/arch/x86/isa/insts | |
| parent | 64d794869271485b79123951d5b198b8a9b12885 (diff) | |
| download | gem5-4e4adcaaa82b8a308bb0752b47ec509fb382e975.tar.xz | |
X86: Set the flags for rotate right with carry instructions.
Diffstat (limited to 'src/arch/x86/isa/insts')
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py index 118afbf9f..baefc0e11 100644 --- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py +++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/rotate.py @@ -236,13 +236,13 @@ def macroop RCL_P_R def macroop RCR_R_I { - rcri reg, reg, imm + rcri reg, reg, imm, flags=(OF,CF) }; def macroop RCR_M_I { ldst t1, seg, sib, disp - rcri t1, t1, imm + rcri t1, t1, imm, flags=(OF,CF) st t1, seg, sib, disp }; @@ -250,19 +250,19 @@ def macroop RCR_P_I { rdip t7 ldst t1, seg, riprel, disp - rcri t1, t1, imm + rcri t1, t1, imm, flags=(OF,CF) st t1, seg, riprel, disp }; def macroop RCR_1_R { - rcri reg, reg, 1 + rcri reg, reg, 1, flags=(OF,CF) }; def macroop RCR_1_M { ldst t1, seg, sib, disp - rcri t1, t1, 1 + rcri t1, t1, 1, flags=(OF,CF) st t1, seg, sib, disp }; @@ -270,19 +270,19 @@ def macroop RCR_1_P { rdip t7 ldst t1, seg, riprel, disp - rcri t1, t1, 1 + rcri t1, t1, 1, flags=(OF,CF) st t1, seg, riprel, disp }; def macroop RCR_R_R { - rcr reg, reg, regm + rcr reg, reg, regm, flags=(OF,CF) }; def macroop RCR_M_R { ldst t1, seg, sib, disp - rcr t1, t1, reg + rcr t1, t1, reg, flags=(OF,CF) st t1, seg, sib, disp }; @@ -290,7 +290,7 @@ def macroop RCR_P_R { rdip t7 ldst t1, seg, riprel, disp - rcr t1, t1, reg + rcr t1, t1, reg, flags=(OF,CF) st t1, seg, riprel, disp }; ''' |