X86: Implement the media shifts that operate on 64 bits or less at a time.

6 files changed, 332 insertions, 18 deletions

diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
index 18d6feb24..617033bc0 100644
--- a/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
+++ b/src/arch/x86/isa/insts/simd128/integer/shift/left_logical_shift.py
@@ -54,8 +54,73 @@
 # Authors: Gabe Black
 
 microcode = '''
-# PSLLW
-# PSLLD
-# PSLLQ
-# PSLLDQ
+def macroop PSLLW_XMM_XMM {
+    msll xmmh, xmmh, xmmlm, size=2, ext=0
+    msll xmml, xmml, xmmlm, size=2, ext=0
+};
+
+def macroop PSLLW_XMM_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msll xmml, xmml, ufp1, size=2, ext=0
+    msll xmmh, xmmh, ufp1, size=2, ext=0
+};
+
+def macroop PSLLW_XMM_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msll xmml, xmml, ufp1, size=2, ext=0
+    msll xmmh, xmmh, ufp1, size=2, ext=0
+};
+
+def macroop PSLLW_XMM_I {
+    mslli xmml, xmml, imm, size=2, ext=0
+    mslli xmmh, xmmh, imm, size=2, ext=0
+};
+
+def macroop PSLLD_XMM_XMM {
+    msll xmmh, xmmh, xmmlm, size=4, ext=0
+    msll xmml, xmml, xmmlm, size=4, ext=0
+};
+
+def macroop PSLLD_XMM_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msll xmml, xmml, ufp1, size=4, ext=0
+    msll xmmh, xmmh, ufp1, size=4, ext=0
+};
+
+def macroop PSLLD_XMM_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msll xmml, xmml, ufp1, size=4, ext=0
+    msll xmmh, xmmh, ufp1, size=4, ext=0
+};
+
+def macroop PSLLD_XMM_I {
+    mslli xmml, xmml, imm, size=4, ext=0
+    mslli xmmh, xmmh, imm, size=4, ext=0
+};
+
+def macroop PSLLQ_XMM_XMM {
+    msll xmmh, xmmh, xmmlm, size=8, ext=0
+    msll xmml, xmml, xmmlm, size=8, ext=0
+};
+
+def macroop PSLLQ_XMM_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msll xmml, xmml, ufp1, size=8, ext=0
+    msll xmmh, xmmh, ufp1, size=8, ext=0
+};
+
+def macroop PSLLQ_XMM_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msll xmml, xmml, ufp1, size=8, ext=0
+    msll xmmh, xmmh, ufp1, size=8, ext=0
+};
+
+def macroop PSLLQ_XMM_I {
+    mslli xmml, xmml, imm, size=8, ext=0
+    mslli xmmh, xmmh, imm, size=8, ext=0
+};
 '''
+# PSLLDQ
diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py
index 63750e292..b88457a02 100644
--- a/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py
+++ b/src/arch/x86/isa/insts/simd128/integer/shift/right_arithmetic_shift.py
@@ -54,6 +54,49 @@
 # Authors: Gabe Black
 
 microcode = '''
-# PSRAW
-# PSRAD
+def macroop PSRAW_XMM_XMM {
+    msra xmmh, xmmh, xmmlm, size=2, ext=0
+    msra xmml, xmml, xmmlm, size=2, ext=0
+};
+
+def macroop PSRAW_XMM_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msra xmml, xmml, ufp1, size=2, ext=0
+    msra xmmh, xmmh, ufp1, size=2, ext=0
+};
+
+def macroop PSRAW_XMM_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msra xmml, xmml, ufp1, size=2, ext=0
+    msra xmmh, xmmh, ufp1, size=2, ext=0
+};
+
+def macroop PSRAW_XMM_I {
+    msrai xmml, xmml, imm, size=2, ext=0
+    msrai xmmh, xmmh, imm, size=2, ext=0
+};
+
+def macroop PSRAD_XMM_XMM {
+    msra xmmh, xmmh, xmmlm, size=4, ext=0
+    msra xmml, xmml, xmmlm, size=4, ext=0
+};
+
+def macroop PSRAD_XMM_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msra xmml, xmml, ufp1, size=4, ext=0
+    msra xmmh, xmmh, ufp1, size=4, ext=0
+};
+
+def macroop PSRAD_XMM_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msra xmml, xmml, ufp1, size=4, ext=0
+    msra xmmh, xmmh, ufp1, size=4, ext=0
+};
+
+def macroop PSRAD_XMM_I {
+    msrai xmml, xmml, imm, size=4, ext=0
+    msrai xmmh, xmmh, imm, size=4, ext=0
+};
 '''
diff --git a/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
index fc6fb180b..c904eaf50 100644
--- a/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
+++ b/src/arch/x86/isa/insts/simd128/integer/shift/right_logical_shift.py
@@ -54,8 +54,73 @@
 # Authors: Gabe Black
 
 microcode = '''
-# PSRLW
-# PSRLD
-# PSRLQ
-# PSRLDQ
+def macroop PSRLW_XMM_XMM {
+    msrl xmmh, xmmh, xmmlm, size=2, ext=0
+    msrl xmml, xmml, xmmlm, size=2, ext=0
+};
+
+def macroop PSRLW_XMM_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msrl xmml, xmml, ufp1, size=2, ext=0
+    msrl xmmh, xmmh, ufp1, size=2, ext=0
+};
+
+def macroop PSRLW_XMM_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msrl xmml, xmml, ufp1, size=2, ext=0
+    msrl xmmh, xmmh, ufp1, size=2, ext=0
+};
+
+def macroop PSRLW_XMM_I {
+    msrli xmml, xmml, imm, size=2, ext=0
+    msrli xmmh, xmmh, imm, size=2, ext=0
+};
+
+def macroop PSRLD_XMM_XMM {
+    msrl xmmh, xmmh, xmmlm, size=4, ext=0
+    msrl xmml, xmml, xmmlm, size=4, ext=0
+};
+
+def macroop PSRLD_XMM_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msrl xmml, xmml, ufp1, size=4, ext=0
+    msrl xmmh, xmmh, ufp1, size=4, ext=0
+};
+
+def macroop PSRLD_XMM_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msrl xmml, xmml, ufp1, size=4, ext=0
+    msrl xmmh, xmmh, ufp1, size=4, ext=0
+};
+
+def macroop PSRLD_XMM_I {
+    msrli xmml, xmml, imm, size=4, ext=0
+    msrli xmmh, xmmh, imm, size=4, ext=0
+};
+
+def macroop PSRLQ_XMM_XMM {
+    msrl xmmh, xmmh, xmmlm, size=8, ext=0
+    msrl xmml, xmml, xmmlm, size=8, ext=0
+};
+
+def macroop PSRLQ_XMM_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msrl xmml, xmml, ufp1, size=8, ext=0
+    msrl xmmh, xmmh, ufp1, size=8, ext=0
+};
+
+def macroop PSRLQ_XMM_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msrl xmml, xmml, ufp1, size=8, ext=0
+    msrl xmmh, xmmh, ufp1, size=8, ext=0
+};
+
+def macroop PSRLQ_XMM_I {
+    msrli xmml, xmml, imm, size=8, ext=0
+    msrli xmmh, xmmh, imm, size=8, ext=0
+};
 '''
+# PSRLDQ
diff --git a/src/arch/x86/isa/insts/simd64/integer/shift/left_logical_shift.py b/src/arch/x86/isa/insts/simd64/integer/shift/left_logical_shift.py
index 4687cab8d..011337ef7 100644
--- a/src/arch/x86/isa/insts/simd64/integer/shift/left_logical_shift.py
+++ b/src/arch/x86/isa/insts/simd64/integer/shift/left_logical_shift.py
@@ -54,7 +54,60 @@
 # Authors: Gabe Black
 
 microcode = '''
-# PSLLW
-# PSLLD
-# PSLLQ
+def macroop PSLLW_MMX_MMX {
+    msll mmx, mmx, mmxm, size=2, ext=0
+};
+
+def macroop PSLLW_MMX_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msll mmx, mmx, ufp1, size=2, ext=0
+};
+
+def macroop PSLLW_MMX_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msll mmx, mmx, ufp1, size=2, ext=0
+};
+
+def macroop PSLLW_MMX_I {
+    mslli mmx, mmx, imm, size=2, ext=0
+};
+
+def macroop PSLLD_MMX_MMX {
+    msll mmx, mmx, mmxm, size=4, ext=0
+};
+
+def macroop PSLLD_MMX_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msll mmx, mmx, ufp1, size=4, ext=0
+};
+
+def macroop PSLLD_MMX_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msll mmx, mmx, ufp1, size=4, ext=0
+};
+
+def macroop PSLLD_MMX_I {
+    mslli mmx, mmx, imm, size=4, ext=0
+};
+
+def macroop PSLLQ_MMX_MMX {
+    msll mmx, mmx, mmxm, size=8, ext=0
+};
+
+def macroop PSLLQ_MMX_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msll mmx, mmx, ufp1, size=8, ext=0
+};
+
+def macroop PSLLQ_MMX_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msll mmx, mmx, ufp1, size=8, ext=0
+};
+
+def macroop PSLLQ_MMX_I {
+    mslli mmx, mmx, imm, size=8, ext=0
+};
 '''
diff --git a/src/arch/x86/isa/insts/simd64/integer/shift/right_arithmetic_shift.py b/src/arch/x86/isa/insts/simd64/integer/shift/right_arithmetic_shift.py
index 63750e292..951b3ea9f 100644
--- a/src/arch/x86/isa/insts/simd64/integer/shift/right_arithmetic_shift.py
+++ b/src/arch/x86/isa/insts/simd64/integer/shift/right_arithmetic_shift.py
@@ -54,6 +54,41 @@
 # Authors: Gabe Black
 
 microcode = '''
-# PSRAW
-# PSRAD
+def macroop PSRAW_MMX_MMX {
+    msra mmx, mmx, mmxm, size=2, ext=0
+};
+
+def macroop PSRAW_MMX_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msra mmx, mmx, ufp1, size=2, ext=0
+};
+
+def macroop PSRAW_MMX_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msra mmx, mmx, ufp1, size=2, ext=0
+};
+
+def macroop PSRAW_MMX_I {
+    msrai mmx, mmx, imm, size=2, ext=0
+};
+
+def macroop PSRAD_MMX_MMX {
+    msra mmx, mmx, mmxm, size=4, ext=0
+};
+
+def macroop PSRAD_MMX_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msra mmx, mmx, ufp1, size=4, ext=0
+};
+
+def macroop PSRAD_MMX_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msra mmx, mmx, ufp1, size=4, ext=0
+};
+
+def macroop PSRAD_MMX_I {
+    msrai mmx, mmx, imm, size=4, ext=0
+};
 '''
diff --git a/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py b/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py
index 1f870dc32..dc6182de7 100644
--- a/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py
+++ b/src/arch/x86/isa/insts/simd64/integer/shift/right_logical_shift.py
@@ -54,7 +54,60 @@
 # Authors: Gabe Black
 
 microcode = '''
-# PSRLW
-# PSRLD
-# PSRLQ
+def macroop PSRLW_MMX_MMX {
+    msrl mmx, mmx, mmxm, size=2, ext=0
+};
+
+def macroop PSRLW_MMX_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msrl mmx, mmx, ufp1, size=2, ext=0
+};
+
+def macroop PSRLW_MMX_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msrl mmx, mmx, ufp1, size=2, ext=0
+};
+
+def macroop PSRLW_MMX_I {
+    msrli mmx, mmx, imm, size=2, ext=0
+};
+
+def macroop PSRLD_MMX_MMX {
+    msrl mmx, mmx, mmxm, size=4, ext=0
+};
+
+def macroop PSRLD_MMX_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msrl mmx, mmx, ufp1, size=4, ext=0
+};
+
+def macroop PSRLD_MMX_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msrl mmx, mmx, ufp1, size=4, ext=0
+};
+
+def macroop PSRLD_MMX_I {
+    msrli mmx, mmx, imm, size=4, ext=0
+};
+
+def macroop PSRLQ_MMX_MMX {
+    msrl mmx, mmx, mmxm, size=8, ext=0
+};
+
+def macroop PSRLQ_MMX_M {
+    ldfp ufp1, seg, sib, disp, dataSize=8
+    msrl mmx, mmx, ufp1, size=8, ext=0
+};
+
+def macroop PSRLQ_MMX_P {
+    rdip t7
+    ldfp ufp1, seg, riprel, disp, dataSize=8
+    msrl mmx, mmx, ufp1, size=8, ext=0
+};
+
+def macroop PSRLQ_MMX_I {
+    msrli mmx, mmx, imm, size=8, ext=0
+};
 '''